P1020NSN2FFB NXP

Freescale Semiconductor Document Number: P1020EC Data Sheet: Technical Data Rev. 1, 03/2012 P1020 P1020 QorIQ Integrated Processor Hardware Specifications One four-channel DMA controller The following list provides an overview of the feature set: 2 Two I C controllers, DUART, timers Dual high-performance 32-bit cores, built on Power Enhanced local bus controller (eLBC) Architecture technology: TDM 36-bit physical addressing 16 general-purpose I/O signals Double-precision floating-point support Operating junction temperature (T ) range: 0125C and 32 Kbyte L1 instruction cache and 32 Kbyte L1 data j 40C to 125C (industrial specification) cache for each core 31 31 mm 689-pin WB-TePBGA II (wire bond 533 MHz to 800 MHz clock frequency temperature-enhanced plastic BGA) 256 Kbyte L2 cache with ECC. Also configurable as SRAM and stashing memory. Three 10/100/1000 Mbps enhanced three-speed Ethernet controllers (eTSECs) TCP/IP acceleration, quality of service, and classification capabilities IEEE 1588 support Lossless flow control MII, RMII, RGMII, SGMII High-speed interfaces supporting various multiplexing options: Four SerDes upto 2.5 GHz/lane multiplexed across controllers Two PCI Express interfaces Two SGMII interfaces High-Speed USB controller (USB 2.0) Host and device support Enhanced host controller interface (EHCI) ULPI interface to PHY Enhanced secure digital host controller (SD/MMC) Enhanced Serial peripheral interface (eSPI) Integrated security engine Protocol support includes ARC4, 3DES, AES, RSA/ECC, RNG, single-pass SSL/TLS XOR acceleration 32-bit DDR2/DDR3 SDRAM memory controller with ECC support Programmable interrupt controller (PIC) compliant with OpenPIC standard 2012 Freescale Semiconductor, Inc. All rights reserved.Table of Contents 1 Pin Assignments and Reset States 4 2.13 Enhanced Local Bus 75 1.1 Ball Layout Diagrams .4 2.14 Enhanced Secure Digital Host Controller (eSDHC) 79 1.2 Pinout Assignments 9 2.15 Programmable Interrupt Controller (PIC) Specifications81 2 Electrical Characteristics 32 2.16 JTAG 82 2.1 Overall DC Electrical Characteristics 32 2.17 I2C 84 2.2 Power Sequencing 36 2.18 GPIO 87 2.3 Power Down Requirements .37 2.19 TDM . 89 2.4 RESET Initialization .37 2.20 High-Speed Serial Interfaces (HSSI) 91 2.5 Power-on Ramp Rate 38 2.21 PCI Express . 97 2.6 Power Characteristics 38 3 Thermal 102 2.7 Input Clocks .40 3.1 Thermal Characteristics . 102 2.8 DDR2 and DDR3 SDRAM 44 3.2 Temperature Diode 102 2.9 eSPI .53 4 Package Information 102 2.10 DUART .55 4.1 Package Parameters for the P1020 WB-TePBGA II . 102 2.11 Ethernet: Enhanced Three-Speed Ethernet (eTSEC) 4.2 Ordering Information . 105 (10/100/1000Mbps)MII/RMII/RGMII/SGMII Electrical 5 Product Documentation 105 Characteristics .56 6 Revision History . 106 2.12 USB 72 P1020 QorIQ Integrated Processor Hardware Specifications, Rev. 1 2 Freescale Semiconductor