Freescale Semiconductor Document Number: P2020EC Data Sheet: Technical Data Rev. 2, 08/2013 P2020 P2020 QorIQ Integrated Processor Hardware WB-TePBGA689 31 mm 31 mm Specifications The following list provides an overview of the P2020 feature Programmable interrupt controller (PIC) compliant with set: OpenPIC standard Two four-channel DMA controllers Dual high-performance Power Architecture e500 cores. 2 Two I C controllers, DUART, timers 36-bit physical addressing Enhanced local bus controller (eLBC) Double-precision floating-point support 16 general-purpose I/O signals 32-Kbyte L1 instruction cache and 32-Kbyte L1 data Operating junction temperature cache for each core 31 31 mm 689-pin WB-TePBGA II (wire bond 800-MHz to 1.33-GHz clock frequency temperature-enhanced plastic BGA) 512 Kbyte L2 cache with ECC. Also configurable as SRAM and stashing memory. Three 10/100/1000 Mbps enhanced three-speed Ethernet controllers (eTSECs) TCP/IP acceleration, quality of service, and classification capabilities IEEE Std 1588 support Lossless flow control R/G/MII, R/TBI, SGMII High-speed interfaces supporting various multiplexing options: Four SerDes to 3.125 GHz multiplexed across controllers Three PCI Express interfaces Two Serial RapidIO interfaces Two SGMII interfaces High-Speed USB controller (USB 2.0) Host and device support Enhanced host controller interface (EHCI) ULPI interface to PHY Enhanced secure digital host controller (SD/MMC) Enhanced Serial peripheral interface (eSPI) Integrated security engine Protocol support includes SNOW, ARC4, 3DES, AES, RSA/ECC, RNG, single-pass SSL/TLS, Kasumi XOR acceleration 64-bit DDR2/DDR3 SDRAM memory controller with ECC support 2011-2013 Freescale Semiconductor, Inc. All rights reserved.Table of Contents 1 Pinout Assignments and Reset States .4 2.13 Enhanced Secure Digital Host Controller (eSDHC) 77 1.1 Ball Layout Diagrams .4 2.14 Programmable Interrupt Controller . 79 1.2 Pinout List by Bus 9 2.15 JTAG 80 2 2 Electrical Characteristics 29 2.16 I C 82 2.1 Overall DC Electrical Characteristics 29 2.17 GPIO 85 2.2 Power Sequencing 33 2.18 High-Speed Serial Interfaces (HSSI) 86 2.3 Power Characteristics 34 2.19 PCI Express . 93 2.4 Input Clocks .35 2.20 Serial RapidIO (SRIO) . 97 2.5 RESET Initialization .39 3 Thermal 101 2.6 Power-on Ramp Rate 40 3.1 Thermal Characteristics . 101 2.7 DDR2 and DDR3 SDRAM 40 3.2 Temperature Diode 102 2.8 eSPI .46 4 Package Information 102 2.9 DUART .48 4.1 Package Parameters for the P2020 WB-TePBGA . 102 2.10 Ethernet: Enhanced Three-Speed Ethernet (eTSEC), 4.2 Ordering Information . 104 MII Management 49 5 Product Documentation 104 2.11 USB 68 6 Revision History . 105 2.12 Enhanced Local Bus .70 P2020 QorIQ Integrated Processor Hardware Specifications, Rev. 2 2 Freescale Semiconductor