Freescale Semiconductor Document Number: P3041EC Data Sheet: Technical Data Rev. 2, 02/2013 P3041 P3041 QorIQ Integrated Processor FC-PBGA1295 Hardware Specifications 37.5 mm x 37.5 mm The P3041 QorIQ integrated processor utilizes four processor Enhanced local bus controller (eLBC) cores built on Power Architecture technology. The cores Four PCI Express 2.0 controllers/ports include high-performance data path acceleration logic and Two serial RapidIO controllers/ports (sRIO port) network and peripheral bus interfaces required for supporting version 1.3 with features from 2.1 networking, telecom/datacom, wireless infrastructure, and Two serial ATA (SATA 2.0) controllers aerospace applications. Enhanced secure digital host controller (SD/MMC) Enhanced serial peripheral interfaces (eSPI) This chip can be used for combined control, data path, and 2 high-speed USB 2.0 controllers with integrated PHYs application layer processing in routers, switches, base station controllers, and general-purpose embedded computing. Its high level of integration offers significant performance benefits compared to multiple discrete devices while also greatly simplifying board design. The chip includes the following functions and features: Four e500mc Power Architecture cores, each with a backside 128 KB L2 cache with ECC Three levels of instructions: User, supervisor, and hypervisor Independent boot and reset Secure boot capability CoreNet fabric supporting coherent and non-coherent transactions amongst CoreNet end-points CoreNet platform cache with ECC CoreNet bridges between the CoreNet fabric the I/Os, datapath accelerators, and high and low speed peripheral interfaces One 10-Gigabit Ethernet (XAUI) controller Five 1-Gigabit Ethernet controllers SGMII interfaces 2.5 Gbps SGMII interfaces RGMII interfaces One 64-bit DDR3 SDRAM memory controller with ECC Multicore programmable interrupt controller 2 Four I C controllers Four 2-pin UARTs or two 4-pin UARTs Two 4-channel DMA engines 20102013 Freescale Semiconductor, Inc. All rights reserved.Table of Contents 2 1 Pin Assignments and Reset States .3 2.17 I C 96 1.1 1295 FC-PBGA Ball Layout Diagrams 3 2.18 GPIO 99 1.2 Pinout List 9 2.19 High-Speed Serial Interfaces (HSSI) . 100 2 Electrical Characteristics 51 3 Hardware Design Considerations 132 2.1 Overall DC Electrical Characteristics 51 3.1 System Clocking 132 2.2 Power-Up Sequencing .56 3.2 Supply Power Default Setting 139 2.3 Power-Down Requirements .58 3.3 Power Supply Design 141 2.4 Power Characteristics 59 3.4 Decoupling Recommendations . 143 2.5 Input Clocks .62 3.5 SerDes Block Power Supply Decoupling 2.6 RESET Initialization .65 Recommendations . 143 2.7 Power-On Ramp Rate 66 3.6 Connection Recommendations . 143 2.8 DDR3 and DDR3L SDRAM Controller .66 3.7 Recommended Thermal Model . 152 2.9 eSPI .75 3.8 Thermal Management Information 153 2.10 DUART .77 4 Package Information 154 2.11 Ethernet: Datapath Three-Speed Ethernet (dTSEC), 4.1 Package Parameters for the FC-PBGA . 154 Management Interface, IEEE Std 1588 .78 4.2 Mechanical Dimensions of the FC-PBGA . 155 2.12 USB 86 5 Security Fuse Processor . 156 2.13 Enhanced Local Bus Interface (eLBC) .87 6 Ordering Information 156 2.14 Enhanced Secure Digital Host Controller (eSDHC) .91 6.1 Part Numbering Nomenclature . 156 2.15 Multicore Programmable Interrupt Controller (MPIC) and 6.2 Orderable Part Numbers Addressed by this Document157 Trust Specifications 93 7 Revision history 158 2.16 JTAG Controller .94 P3041 QorIQ Integrated Processor Hardware Specifications, Rev. 2 2 Freescale Semiconductor