QorIQ Communications Platforms P4 Series Multicore Processors Overview Freescale QorIQ communications platforms are the next-generation evolution of our leading PowerQUICC communications processors. Built using high- performance Power Architecture cores, QorIQ platforms enable a new era of networking innovation where the reliability, security and quality of service for every connection matters. in 45 nm technology, is designed to deliver QorIQ P4080 Multicore Processor high-performance, next-generation networking The QorIQ P4080 multicore processor, the services in a very low power envelope. first product offered in the QorIQ P4 platform series, delivers industry-leading performance The QorIQ P4080 processor is designed for in the under 30-watt power category. It combined control and dataplane processing, combines eight Power Architecture e500mc enabling high-performance layers 27 cores operating at frequencies up to 1.5 GHz processing. Its high level of integration offers with high-performance datapath acceleration significant performance benefits compared to logic, as well as networking I/O and other multiple discrete devices, while also greatly peripheral bus interfaces. The P4080, built simplifying board design. QorIQ P4080/P4040/P4081 Block Diagram QorIQ P4080/P4040/P4081 Block Diagram 1024 KB 64-bit Power Architecture CoreNet DDR2/3 e500mc Core Platform Cache Memory Controller with ECC 128 KB Backside L2 Cache 1024 KB 64-bit 32 KB 32 KB CoreNet DDR2/3 D-Cache I-Cache Platform Cache Memory Controller with ECC Security Fuse Processor CoreNet Coherency Fabric Security Monitor Peripheral Access PAMU PAMU PAMU PAMU Management Unit 2x USB 2.0 w/ULPI eLBC Frame Manager Frame Manager Real-Time Debug Queue 2x DMA SEC Watchpoint Power Management Mgr. 4.0 Parse, Classify, Parse, Classify, Cross Trigger SD/MMC Distribute Distribute Perf. 2x DUART Trace PCIe PCIe PCIe sRIO sRIO Monitor PME Buffer 2 1 G 1 G 1 G 1 G 4x I C Mgr. 2.0 10 G 10 G Aurora 1 G 1 G 1 G 1 G SPI, GPIO 18 Lanes, 5 GHz SerDes Core Complex (CPU, L2 and Frontside CoreNet Platform Cache) P4080 and P4081 Only Accelerators and Memory Control Networking Elements P4080 and P4040 Only Basic Peripherals and InterconnectThe processor is well suited for applications Advanced virtualization technology brings a QorIQ P4080 Technical that are highly compute intensive, I/O new level of hardware partitioning through Specifications intensive or both. This makes it ideal for an embedded hypervisor that allows system Eight high-performance Power Architecture applications such as enterprise and service developers to ensure software running on any e500mc cores, each with a 32 KB provider routers, switches, media gateways, CPU only accesses the resources (memory, instruction and data L1 cache and a base station controllers, radio network peripherals, etc.) that it is explicitly authorized private 128 KB L2 cache controllers (RNCs), access gateways for to access. The embedded hypervisor enables Three levels of instruction: user, long-term evolution (LTE) and general- safe and autonomous operation of multiple supervisor and hypervisor purpose embedded computing systems in individual operating systems, allowing them to Independent boot and reset the networking, telecom, industrial, aerospace share system resources, including processor and defense markets. cores, memory and other on-chip functions. Secure boot capability 2 MB shared L3 CoreNet platform cache Key Features Ecosystem and Developer Hierarchical interconnect fabric Environment Freescale delivers a groundbreaking three- CoreNet fabric supporting coherent tiered cache hierarchy on the QorIQ P4 Developers creating solutions with Power and non-coherent transactions with platform. Each core has an integrated level 1 Architecture technology have long benefited prioritization and bandwidth allocation (L1) cache as well as a dedicated level 2 (L2) from a vibrant support ecosystem, including amongst CoreNet end points backside cache that can significantly improve high-quality tools, OSes and network protocol 800 Gb/s coherent read bandwidth performance. Finally, a multi-megabyte level 3 stacks. Freescale has collaborated with our (L3) cache is also provided for those tasks for partners on the QorIQ P4080 processor to Queue manager fabric supporting which a shared cache is desirable. continue our strong ecosystem heritage. This packet-level queue management and helps to ensure that the best enablement quality of service scheduling The CoreNet coherency fabric is a key design tools are available to cost-effectively meet the component of the QorIQ P4 platform. It Two 64-bit DDR2/DDR3 SDRAM unique development challenges of multicore manages full coherency of the caches and memory controllers with ECC and architectures and speed your time to market. provides scalable on-chip, point-to-point interleaving support To this end, Freescale has partnered with Datapath acceleration architecture connectivity supporting concurrent traffic to Virtutech to offer a robust, innovative hybrid incorporating acceleration for the and from multiple resources connected to the simulation environment that provides a following functions: fabric, eliminating single-point bottlenecks controlled, deterministic and fully reversible Packet parsing, classification and for non-competing resources. This eliminates environment for the development, debugging distribution bus contention and latency issues associated and benchmarking of software for complex with scaling shared bus/shared memory Queue management for scheduling, multicore-based architectures. The hybrid architectures that are common in other packet sequencing and congestion simulator combines Virtutechs fast, functional multicore approaches. management Simics model, with a detailed performance The QorIQ P4080 multicore processor is Hardware buffer management for model of the platform. This combination extremely flexible and can be configured buffer allocation and de-allocation enables fast hardware concept testing and to meet many system application needs. evaluation, as well as performance verification Cryptographic security acceleration The processors e500mc cores, leveraging and helps accelerate your development cycle, (SEC 4.0) advanced virtualization technology, can work as provide more flexible debug capability and eight symmetric multiprocessing (SMP) cores, RegEx pattern matching (PME 2.0) improve the overall quality of your software. or eight completely asymmetric multiprocessing Ethernet interfaces Freescale has also engineered capabilities (AMP) cores, or they can be operated with Two 10 Gb/s Ethernet (XAUI) into the QorIQ P4080 to enable advanced varying degrees of independence with a controllers debugging while working in tandem with combination of SMP and AMP groupings. Full its ecosystem partners to assure availability Eight 1 Gb/s Ethernet (SGMII) processor independence, including the ability of tools that can take advantage of these controllers to independently boot and reset each e500mc features. These capabilities include integrated core, is a defining characteristic of the device. High-speed peripheral interfaces instruction trace, watchpoint triggers, cross- The ability of the cores to run different operating Three PCI Express V2.0 controllers/ event triggers, performance monitoring and systems (OS), or run OS-less, provides the user ports running at up to 5 GHz other debug features as defined by the with significant flexibility in partitioning between Power ISA. These features enable dynamic Two Serial RapidIO 1.2 controllers/ control, datapath and applications processing. debug essential for providing visibility into ports running at up to 3.125 GHz It also simplifies consolidation of functions complex interactions that may occur among previously spread across multiple discrete tasks running on different cores. processors onto a single device.