PCA9537 2 4-bit I C-bus and SMBus low power I/O port with interrupt and reset Rev. 05 7 May 2009 Product data sheet 1. General description The PCA9537 is a 10-pin CMOS device that provides 4 bits of General Purpose parallel 2 Input/Output (GPIO) expansion with interrupt and reset for I C-bus/SMBus applications 2 and was developed to enhance the NXP Semiconductors family of I C-bus I/O expanders. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push-buttons, LEDs, fans, etc. The PCA9537 consists of a 4-bit Conguration register (input or output selection), 4-bit Input Port register, 4-bit Output Port register and a 4-bit Polarity Inversion register (active HIGH or active LOW operation). The system master can enable the I/Os as either inputs or outputs by writing to the I/O conguration bits. The data for each input or output is kept in the corresponding Input Port or Output Port register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master. The PCA9537 open-drain interrupt output (INT) is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. The RESET pin causes the same reset/initialization to occur without de-powering the device. 2 2 The I C-bus address is xed and allows only one device on the same I C-bus/SMBus. 2. Features 2 n 4-bit I C-bus GPIO with interrupt and reset n Operating power supply voltage range of 2.3 V to 5.5 V n 5 V tolerant I/Os n Polarity Inversion register n Active LOW interrupt output n Active LOW reset input n Low standby current n Noise lter on SCL/SDA inputs n No glitch on power-up n Internal power-on reset n 4 I/O pins that default to 4 inputs n 0 Hz to 400 kHz clock frequency n ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101PCA9537 NXP Semiconductors 2 4-bit I C-bus and SMBus low power I/O port with interrupt and reset n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA n Offered in TSSOP10 package 3. Ordering information Table 1. Ordering information T = - 40 C to +85 C amb Type number Topside Package mark Name Description Version PCA9537DP 9537 TSSOP10 plastic thin shrink small outline package SOT552-1 10 leads body width 3 mm 4. Block diagram PCA9537 IO0 SCL INPUT IO1 SDA FILTER 4-bit IO2 INPUT/ 2 IO3 I C-BUS/SMBus OUTPUT CONTROL PORTS write pulse V DD POWER-ON read pulse RESET RESET V DD V SS INT LP FILTER 002aae634 Remark: All I/Os are set to inputs at reset. Fig 1. Block diagram of PCA9537 PCA9537 5 NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 7 May 2009 2 of 24