PCA9663B,118 NXP

PCA9663 2 Parallel bus to 3 channel Fm+ I C-bus controller Rev. 1.2 14 December 2016 Product data sheet 1. General description 2 The PCA9663 is an advanced single master mode I C-bus controller. It is a fourth 2 generation bus controller designed for data intensive I C-bus data transfers. It has three 2 independent I C-bus channels with data rates up to 1 Mbits/s using the Fast-mode Plus (Fm+) open-drain topology. Each channel has a generous 4352 byte data buffer which makes the PCA9663 the ideal companion to any CPU that needs to transmit and receive large amounts of serial data. 2 The PCA9663 is a 8-bit parallel-bus to I C-bus protocol converter. Each channel can be configured to communicate with up to 64 slaves in one serial sequence with no intervention from the CPU. The controller also has a sequence loop control feature that allows it to automatically retransmit a stored sequence. 2 Its onboard oscillator and PLL allow the controller to generate the clocks for the I C-bus and for the interval timer used in sequence looping. This feature greatly reduces CPU overhead when data refresh is required in fault tolerant applications. An external trigger input allows data synchronization with external events. The trigger 2 signal controls the rate at which a stored sequence is re-transmitted over the I C-bus. Error reporting is handled at the transaction level, channel level and controller level with a simple interrupt tree and interrupt masks allow further customization of interrupt management. 2 The controller and parallel bus interfaces run at 3.3 V and the I C-bus I/Os are 5 V tolerant with logic levels referenced to a dedicated V input pin with a range of 3.0 V DD(IO) to 5.5 V. 2. Features and benefits 2 Parallel-bus to I C-bus protocol converter and interface 1 Mbit/s and up to 30 mA SCL/SDA I Fast-mode Plus (Fm+) capability OL Internal oscillator trimmed to 1 % accuracy reduces external components Individual 4352-byte buffers for the Fm+ channels for a total of 13056 bytes of buffer space Three levels of reset: individual software reset, global software reset, global hardware RESET pin Communicates with up to 64 slaves on each channel in one serial sequence Sequence looping with interval timer Supports SCL clock stretching JTAG port available for boundary scan testing during board manufacturing process Trigger input synchronizes serial communication exactly with external eventsPCA9663 NXP Semiconductors 2 Parallel bus to 3 channel Fm+ I C-bus controller Maskable interrupts 2 Fast-mode Plus I C-bus capable and compatible with SMBus Operating supply voltage: 3.0 V to 3.6 V (device and host interface) 2 I C-bus I/O supply voltage: 3.0 V to 5.5 V Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA ESD protection exceeds 8000 V HBM per JESD22-A114, and 1000 V CDM per JESD22-C101 Packages offered: LQFP48 3. Applications 2 Add I C-bus port to controllers/processors that do not have one 2 2 Add additional I C-bus ports to controllers/processors that need multiple I C-bus ports Converts 8 bits of parallel data to serial data stream to prevent having to run a large number of traces across the entire printed-circuit board Entertainment systems LED matrix control 2 Data intensive I C-bus transfers 4. Ordering information Table 1. Ordering information Type number Topside Package marking Name Description Version PCA9663B PCA9663 LQFP48 plastic low profile quad flat package 48 leads SOT313-2 body 7 7 1.4 mm 4.1 Ordering options Table 2. Ordering options Type number Orderable Package Packing method Minimum Temperature part number order quantity PCA9663B PCA9663B,118 LQFP48 REEL 13 Q1/T1 2000 T = 40 C to +85 C amb *STANDARD MARK SMD PCA9663 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet Rev. 1.2 14 December 2016 2 of 68