PN5120A0ETC2QL NXP

PN512 Full NFC frontend Rev. 5.3 17 March 2020 Product data sheet 111353 COMPANY PUBLIC 1. General description PN512 is the most broadly adopted NFC frontend - powering more than 10 billion NFC transactions per year. It is a highly integrated NFC frontend for contactless communication at 13.56 MHz. This NFC frontend utilizes an outstanding modulation and demodulation concept completely integrated for different kinds of contactless communication methods and protocols at 13.56 MHz. The PN512 NFC frontend supports 4 different operating modes Reader/Writer mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme Reader/Writer mode supporting ISO/IEC 14443B Card Operation mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme NFCIP-1 mode Enabled in Reader/Writer mode for ISO/IEC 14443A/MIFARE, the PN512s internal transmitter part is able to drive a reader/writer antenna designed to communicate with ISO/IEC 14443A/ MIFARE cards and transponders without additional active circuitry. The receiver part provides a robust and efficient implementation of a demodulation and decoding circuitry for signals from ISO/IEC 14443A/MIFARE compatible cards and transponders. The digital part handles the complete ISO/IEC 14443A framing and error detection (Parity and CRC). Enabled in Reader/Writer mode for FeliCa, the PN512 NFC frontend supports the FeliCa communication scheme. The receiver part provides a robust and efficient implementation of the demodulation and decoding circuitry for FeliCa coded signals. The digital part handles the FeliCa framing and error detection like CRC. The PN512 supports contactless communication using FeliCa Higher transfer speeds up to 424 kbit/s in both directions. The PN512 supports all layers of the ISO/IEC 14443B reader/writer communication scheme, given correct implementation of additional components, like oscillator, power supply, coil etc. and provided that standardized protocols, e.g. like ISO/IEC 14443-4 and/or ISO/IEC 14443B anticollision are correctly implemented. In Card Operation mode, the PN512 NFC frontend is able to answer to a reader/writer command either according to the FeliCa or ISO/IEC 14443A/MIFARE card interface scheme. The PN512 generates the digital load modulated signals and in addition with an external circuit the answer can be sent back to the reader/writer. A complete card 2 functionality is only possible in combination with a secure IC using the S C interface.PN512 NXP Semiconductors Full NFC frontend Additionally, the PN512 NFC frontend offers the possibility to communicate directly to an NFCIP-1 device in the NFCIP-1 mode. The NFCIP-1 mode offers different communication mode and transfer speeds up to 424 kbit/s according to the Ecma 340 and ISO/IEC 18092 NFCIP-1 Standard. The digital part handles the complete NFCIP-1 framing and error detection. Various host controller interfaces are implemented: 1 8-bit parallel interface SPI interface serial UART (similar to RS232 with voltage levels according pad voltage supply) 2 I C interface. 1.1 Different available versions The PN512 is available in three versions: PN5120A0HN1/C2 (HVQFN32), PN5120A0HN/C2 (HVQFN40) and PN5120A0ET/C2 (TFBGA64), hereafter named as version 2.0 PN512AA0HN1/C2 (HVQFN32) and PN512AA0HN1/C2BI (HVQFN32 with Burn In), hereafter named as industrial version, fulfilling the automotive qualification stated in AEC-Q100 grade 3 from the Automotive Electronics Council, defining the critical stress test qualification for automotive integrated circuits (ICs). The customer recognizes that: since the product was not originally designed for automotive use, it will not be possible to achieve the levels of quality and failure analysis that are normally associated with products explicitly designed for automotive use. the product qualification conforms to AEC-Q100. all product production locations are certified according to TS16949. PN5120A0HN1/C1(HVQFN32) and PN5120A0HN/C1 (HVQFN40), hereafter named as version 1.0 The data sheet describes the functionality for the industrial version and version 2.0. The differences of the version 1.0 to the version 2.0 are summarized in Section 20. The industrial version has only differences within the outlined characteristics and limitations. 1. 8-bit parallel Interface only available in HVQFN40 package. PN512 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2020. All rights reserved. Product data sheet Rev. 5.3 17 March 2020 COMPANY PUBLIC 111353 2 of 137