PTN3381D Enhanced performance HDMI/DVI level shifter with voltage regulator, dongle detection and supporting 3 Gbit/s operation Rev. 2 26 July 2012 Product data sheet 1. General description The PTN3381D is a high-speed level shifter device which converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.4b compliant open-drain current-steering differential output signals, up to 3 Gbit/s to support 36-bit deep color, 3D and 3 Gbit/s modes. Each of these channels provides a level-shifting differential buffer to translate from low-swing AC-coupled differential signaling on the source side, to TMDS-type DC-coupled differential current-mode signaling terminated into 50 to 3.3 V on the sink side. Additionally, the PTN3381D provides a single-ended active buffer for voltage translation of the HPD signal from 5 V on the sink side to 3.3 V on the source side and provides a channel with active buffering and level shifting of the DDC channel (consisting of a clock and a data line) between 3.3 V source-side and 5 V sink-side. The 2 DDC channel is implemented using active I C-bus buffer technology providing capacitive isolation, redriving and level shifting as well as disablement (isolation between source and sink) of the clock and data lines. To provide the highest level of integration in external adapter (or: dongle) applications, PTN3381D includes an on-board 5 V DC regulator. Its output is designed to provide the required 5 V power supply to the DVI or HDMI connector, thereby eliminating the need for a separate external regulator. The on-board regulator needs only two external capacitors to operate, and its output is active whenever a valid 3.3 V is applied to the PTN3381D V DD pins. The low-swing AC-coupled differential input signals to the PTN3381D typically come from a display source with multi-mode I/O, which supports multiple display standards, for example, DisplayPort, HDMI and DVI. While the input differential signals are configured to carry DVI or HDMI coded data, they do not comply with the electrical requirements of the DVI v1.0 or HDMI v1.3a specification. By using PTN3381D, chip set vendors are able to implement such reconfigurable I/Os on multi-mode display source devices, allowing the support of multiple display standards while keeping the number of chip set I/O pins low. See Figure 1. The PTN3381D main high-speed differential lanes feature low-swing self-biasing differential inputs which are compliant to the electrical specifications of DisplayPort Standard v1.2 and/or PCI Express Standard v1.1, and open-drain current-steering differential outputs compliant to DVI v1.0 and HDMI v1.4b electrical specifications. The 2 I C-bus channel actively buffers as well as level-translates the DDC signals for optimal 2 capacitive isolation. Its I C-bus control block also provides for optional software HDMI dongle detect by issuing a predetermined code sequence upon a read command to an 2 I C-bus specified address. The PTN3381D also supports power-saving modes in order to minimize current consumption when no display is active or connected.PTN3381D NXP Semiconductors Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation The PTN3381D is a fully featured HDMI as well as DVI level shifter. It is functionally equivalent to PTN3361D but provides an onboard 5 V regulator. The PTN3381D supersedes PTN3381B, and provides a better high speed performance with a programmable equalizer. PTN3381D is powered from a single 3.3 V power supply consuming a small amount of power (230 mW typical with no load at 5 V regulator) and is offered in a 48-terminal HVQFN48 package. MULTI-MODE DISPLAY SOURCE OE N PTN3381D reconfigurable I/Os PHY ELECTRICAL AC-coupled OUT D4+ TMDS differential pair OUT D4 coded output buffer TMDS data TX data IN D4+ FF DATA LANE IN D4 TX AC-coupled OUT D3+ TMDS differential pair OUT D3 coded output buffer TMDS data TX IN D3+ data FF DATA LANE IN D3 TX AC-coupled OUT D2+ TMDS differential pair OUT D2 coded output buffer TMDS data TX IN D2+ data FF DATA LANE IN D2 TX AC-coupled OUT D1+ TMDS differential pair OUT D1 clock output buffer clock TX pattern IN D1+ CLOCK LANE FF IN D1 TX 0 V to 3.3 V 0 V to 5 V HPD SOURCE HPD SINK quinary input EQ5 DDC EN 3.3 V (0 V to 3.3 V) 3.3 V 5 V 3.3 V DDET SCL SOURCE SCL SINK 3.3 V 5 V DDC I/O 2 (I C-bus) CONFIGURATION SDA SOURCE SDA SINK 5 V out DC V5OUT 002aaf310 Remark: TMDS clock and data lanes can be assigned arbitrarily and interchangeably to D 4:1 . Fig 1. Typical application system diagram PTN3381D All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 2 26 July 2012 2 of 30 DVI/HDMI CONNECTOR