SC16C2552B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Rev. 03 12 February 2009 Product data sheet 1. General description The SC16C2552B is a two channel Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel data into serial data, and vice versa. The UART can handle serial data rates up to 5 Mbit/s. The SC16C2552B is pin compatible with the PC16552 and ST16C2552. The SC16C2552B provides enhanced UART functions with 16-byte FIFOs, modem control interface, DMA mode data transfer and concurrent writes to control registers of both channels. The DMA mode data transfer is controlled by the FIFO trigger levels and the RXRDY and TXRDY signals. On-board status registers provide the user with error indications and operational status. System interrupts and modem control features may be tailored by software to meet specic user requirements. An internal loopback capability allows on-board diagnostics. Independent programmable baud rate generators are provided to select transmit and receive baud rates. The SC16C2552B operates at 5 V, 3.3 V and 2.5 V and the industrial temperature range, and is available in a plastic PLCC44 package. 2. Features n Industrial temperature range (- 40 C to +85 C) n 5 V, 3.3 V and 2.5 V operation n Pin-to-pin compatible to PC16C552, ST16C2552 n Up to 5 Mbit/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V 1 n 5 V tolerant on input only pins n 16-byte transmit FIFO n 16-byte receive FIFO with error ags n Independent transmit and receive UART control n Four selectable receive FIFO interrupt trigger levels xed transmit FIFO interrupt trigger level n Modem control functions (CTS, RTS, DSR, DTR, RI, CD) n DMA operation and DMA monitoring via package I/O pins, TXRDY/RXRDY n UART internal register sections A and B may be written to concurrently n Multi-function output allows more package functions with fewer I/O pins n Programmable character lengths (5, 6, 7, 8), with even, odd, or no parity 1. For data bus pins D7 to D0, see Table 23 Limiting values.SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 3. Ordering information Table 1. Ordering information Type number Package Name Description Version SC16C2552BIA44 PLCC44 plastic leaded chip carrier 44 leads SOT187-2 4. Block diagram SC16C2552B TRANSMIT TRANSMIT FIFO SHIFT TXA, TXB REGISTERS REGISTER D0 to D7 DATA BUS IOR AND IOW CONTROL RESET LOGIC RECEIVE RECEIVE FIFO SHIFT RXA, RXB REGISTERS REGISTER A0 to A2 REGISTER CS SELECT CHSEL LOGIC DTRA, DTRB RTSA, RTSB MFA, MFB MODEM CONTROL CTSA, CTSB LOGIC INTA, INTB CLOCK AND INTERRUPT RIA, RIB TXRDYA, TXRDYB BAUD RATE CONTROL CDA, CDB RXRDYA, RXRDYB GENERATOR LOGIC DSRA, DSRB 002aaa487 XTAL1 XTAL2 Fig 1. Block diagram of SC16C2552B SC16C2552B 3 NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 12 February 2009 2 of 38 INTERCONNECT BUS LINES AND CONTROL SIGNALS