SCP2207VMU NXP

Freescale Semiconductor Document Number: SCP220x Rev. 2.1, 06/2015 Data Sheet: Product Preview SCP220x SCP220x ICP Family Data Sheet 1 Introduction .1 1 Introduction 1.1 The SCP220x function blocks .2 1.2 SCP220x Features 2 The SCP220x is a family of highly-programmable Image 2 SCP220x Architecture Overview .4 2.1 Voltage islands .5 Cognition Processors (ICP) enabling imaging and video 2.2 Blocks .5 applications for automotive smart cameras, video 2.3 Buses and DMA 6 2.4 Pin Configuration .7 surveillance cameras and consumer devices such as 3 System Design Considerations 8 3.1 Core and I/O Power .8 personal media players. The ICPs of the SCP220x family 3.2 PLL and Timing Generation 10 are programmable system-on-chip (SoC) featuring 3.3 Clock Configuration 12 3.4 External Memory Interface .16 CogniVues patented APEX technology providing high 3.5 Reset .16 computing performance at low power in a small package 3.6 Boot-up .17 3.7 Low Power Configurations .20 size. 4 Interconnect and Communication .21 4.1 NAND Flash Interface 21 The SCP220x family comprises: 4.2 UART .24 4.3 SPI .26 SCP2201 Equipped with 128 Mbit (16 MB) of 4.4 Sensor Interface (SIF) 29 4.5 Display Sub-System (DSS) 30 stacked Mobile DDR SDRAM in package 4.6 USB 2.0 HIGH SPEED .35 4.7 Audio Interface 36 SCP2207 Equipped with 512 Mbit (64 MB) of 4.8 Media Storage MMC and MMCPlus blocks (compatible SD/SDHC) .42 stacked Mobile DDR SDRAM in package 4.9 I2C Interface .45 4.10 Pulse Width Modulated Outputs 50 4.11 KeyPad Scan Interface 53 4.12 GPIOs and Alternate Functions .54 4.13 Production Test and System Signals .61 5 Registers 61 5.1 Memory Map .61 5.2 Clock Configuration Registers 64 5.3 PAD and I/O registers 71 5.4 Reset and Clock Gating .78 5.5 Miscellaneous 82 5.6 Memory Controller .83 5.7 NAND Interface Registers Description 95 5.8 UART Control Registers 110 5.9 SPI Registers 117 5.10 Audio Registers 126 5.11 MMC/SD Control Registers .136 5.12 MMCPlus Control Registers .145 5.13 I2C Registers 154 5.14 PWM Registers 158 5.15 KeyScan Registers 162 5.16 GPIO Registers 165 6 Packaging 168 6.1 SCP2201 .168 6.2 SCP2207 .169 6.3 SCP220x Pinout 170 7 Electrical Specifications 180 7.1 Absolute Maximum Rating 180 7.2 Recommended Operating Ranges .180 7.3 Thermal Characteristics 181 7.4 DC Characteristics 181 8 Revision History 183 Freescale Semiconductor, Inc., 2015Introduction 1.1 The SCP220x function blocks SCP220x APEX Core USB 2.0 Camera OTG APU (96 CU + 96 CMEM) Sensor Interface .... CU CU CU CU CU CU CU CU CU CU CU CU CU CU CU CU CU CU CU NAND or Array Controller Processor MoviNAND Display Interface Interface Multi Sequencer Channel RISC DMA Stream DMA MicroSD/ SDHC TV Out Main Processor - ARM9 Memory Controller Mobile DDR SDRAM 2 KeyPad I S / AC97 (stacked) Power Manager SPI 2 I C UART PWM GPIO Master/ Slave Figure 1. SCP220x Image Cognition Processors 1.2 SCP220x Features 1.2.1 SCP220x General Features CogniVue APEX Processor programmable 34Billion-Operations per second Vision Processor with patented massively parallel Array Processor Unit (APU) with 96 Computing Units (CUs) with dedicated memory, discreet RISC processor, H/W acceleration blocks, wide-bandwidth stream DMAs and internal 64-bit data buses ARM926EJ-S RISC processor with 16 KB of instruction cache (I-cache) and 16 KB of data cache (D-cache) Multiple power domains for different peripheral IOs 1.2.2 Interconnect and Communication 1.2.2.1 Video Processing Fully-programmable Array Processor (APEX) for running video/image processing algorithms Video codecs support diverse resolutions at 30 fps with 4 Mbps maximum bitrate Supported video decoding standards: MPEG-4 Simple Profile and Advanced Simple Profile supports 720x480 at 30 fps For other standards consult factory Supported video encoding standard is MPEG-4 Simple Profile, 720x480 at 30 fps SCP220x ICP Family, Rev.2.1 2 Freescale Semiconductor CMEM CMEM CMEM CMEM CMEM CMEM CMEM CMEM CMEM CMEM CMEM CMEM CMEM CMEM CMEM CMEM CMEM CMEM CMEM