LINEOUT R HHPP RR LINEOUT R Document Number: SGTL5000 NXP Semiconductors Rev. 7, 1/2022 Data Sheet: Technical Data Low Power Stereo Codec with SGTL5000 Headphone Amp The SGTL5000 is a Low Power Stereo Codec with Headphone Amp from NXP, and is designed to provide a complete audio solution for products needing LINEIN, MIC IN, LINEOUT, headphone-out, and AUDIO CODEC digital I/O. Deriving its architecture from best in class, NXP integrated products that are currently on the market. The SGTL5000 is able to achieve ultra low power with very high performance and functionality, all in one of the smallest footprints available. Target markets include media players, navigation devices, smart phones, tablets, medical equipment, exercise equipment, consumer audio equipment, etc. Features such as capless headphone design and an internal PLL help lower overall system cost. Features PB-FREE PB-FREE PB-FREE 98ARE10742D 98ARE10739D 98ASA01814D Analog Inputs 20-PIN QFN 32-PIN QFN 32-PIN QFN Stereo LINEIN - Support for external analog input Stereo LINEIN - Codec bypass for low power SGTL5000XNLA3 SGTL5000XNBA3 SGTL5000XNAA3 MIC bias provided Programmable MIC gain ADC - 85 dB SNR (-60 dB input) and -73 dB THD+N ORDERING INFORMATION (VDDA = 1.8 V) Temperature Analog Outputs Device Package Range (T ) A HP Output - Capless design HP Output - 62.5 mW max, 1.02 kHz sine into 16 load at 3.3 V SGTL5000XNLA3/R2 20 Sawn QFN HP Output - 100 dB SNR (-60 dB input) and -80 dB THD+N SGTL5000XNAA3/ 32 Punch QFN (V = 1.8 V, 16 load, DAC to headphone) DDA -40 to 85 C (1) R2 LINEOUT - 100 dB SNR (-60 dB input) and -85 dB THD+N (V = 3.3 V) SGTL5000XNBA3/R2 DDIO 32 Sawn QFN Digital I/O Notes 2 I S port to allow routing to Application Processor 1. SGTL5000XNAA3/R2 will undergo End-of-Life / Integrated Digital Processing Product Discontinuation by end of Q1 2022. NXP surround, NXP bass, tone control/ parametric equalizer/ graphic equalizer clocking/control PLL allows input of an 8.0 MHz to 27 MHz system clock - standard audio clocks are derived from PLL Power Supplies Designed to operate from 1.62 to 3.6 volts LILINNEEIINN R R AAnnalalogog I Inn MMPP3/3/FFMM I Innputput LILINNEEIINN L L (S(Stteerreeoo LLiinnee In In, , MIMICC IINN MMIICC I INN//SSppeech eech MIMICC)) HHeadeadphonephone // ADADCC DADACC RReecogncogniittiioonn MMIICC BIBIASAS LLiine One Ouutt HHeadpheadphoneone HPHP LL w/w/ v voolluummee I2I2S S DDIINN II22SS LLRCLRCLKK AApplppliiccatatiion on I2I2SS AAudiudioo SpSpeeaakkeerr InInteterrffaaccee SwSwiittcchh PPrrocessocessoorr I2I2S S SCSCLLKK AAmmpp//DDoocckkiing ng SSttaattiioonn//FMFMTXTX I2I2SS DDOOUUTT AAudiudioo PPrrococesesssiingng PLPLLL SYSSYS MMCCLLKK II22CC//SPISPI C Coonnttrrooll Note: SPI is not supported in the 3.0 mm x 3.0 mm 20-pin QFN package Figure 1. SGTL5000 Simplified Application Diagram 2021 NXP B.V. LLIINNEEOOUUTT LLINTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM Analog Gain Digital Gain Headphone Volume Control -52dB to +12dB HP OUT LINE IN Analog DAC Volume (CHIP ANA HP CTRL) Gain ADC Control DAC MIC GAIN (0 to -90dB to 0dB MIC IN (0dB, 20dB, 22.5dB) 30dB, 40dB) Audio Switch I2S DIN Line Out Volume Control LINEOUT I2S DOUT (CHIP LINE OUT VOL) Mix AVC Bass Enhancement Tone Control /GEQ/PEQ Surround +6dB +12dB +6dB +12dB Only Gain is shown for the Digital Audio Processing blocks. For complete description please see Digital Audio Processing section. Figure 2. SGTL5000 Simplified Internal Block Diagram SGTL5000 2 NXP Semiconductors