QorIQ Communications Platforms T Seriesi.MX 6SoloX QorIQ T1040/20 and applications processors T1042/22 and could communication prbe on two lines ocessors The QorIQ T1 family of communications processors combines up to four 64-bit cores, built on Power Architecture technology, with high-performance Data Path Acceleration Architecture (DPAA) and network peripheral bus interfaces required for networking and telecommunications. OVERVIEW TARGET MARKETS AND APPLICATIONS This scalable, pin-compatible family features the industrys The T1 family is ideally suited for use in mixed control first 64-bit embedded processor with an integrated Gigabit and data plane applications such as fixed routers, switches, Ethernet switch, the T1040 (and dual-core T1020), which Internet access devices, firewall and other packet filtering simplifies hardware design, reduces power and overall applications, as well as general-purpose embedded system cost. computing. Its high level of integration offers significant performance benefits and greatly helps to simplify board design. Enterprise equipment: Fixed routers, Ethernet switches, UTM equipment Service provider: Edge routers, mobile backhaul Aerospace, defense and government: Ruggedized network appliances Industrial computing: Single board computers, factory automation, smart gride5500 CORE QorIQ T1040 AND T1042 COMMUNICATIONS PROCESSORS The T1 family is based on the 64-bit e5500 Power Architecture core, which Power Architecture e5500 256 KB uses a seven-stage pipeline for low Backside L2 Cache 32/64-bit latency response to unpredictable 32 KB 32 KB 256 KB DDR3L/4 D Cache I Cache Platform Cache Memory Controller code execution paths, boosting single- TM threaded performance. Security Fuse Processor CoreNet Coherency Fabric Peripheral Access Security Monitor PAMU PAMU PAMU PAMU Mgmt. Unit e5500 Core Features Power Management Real-Time Debug QUICC Parse, Classify, Distribute T1040: Supports up to 1.5 GHz core Engine Security 5.4 Queue 2x DMA, SDXC/eMMC Warchpoint 1 GbE 1 GbE (XoR CRC) Mgr. 1 GbE T1042: Cross Trigger frequencies 2x DUART T1042/T1022 Only 1 GbE 1 GbE 4x DMA Perf. 2 4x I S Tightly coupled low latency cache 8 Port Switch Trace Monitor T1040/ Pattern 1 GbE 1 GbE 1 GbE 1 GbE T1020 2 Buffer 4x I S Match hierarchy Mgr. Only Aurora 1 GbE 1 GbE 1 GbE 1 GbE Engine 2.0 2x USB 2.0 w/PHY 32 KB I/D (L1), 256 KB L2 per core 8-Lane 5 GHz SerDes DIU Up to 256 KB of shared platform Core Complex Complex (CPU, U2, L3 Cache) Basic Peripherals and Interconnect cache (L3) Accelerators and Memory Control Networking Elements 3.0 DMIPS/MHz per core Up to 64 GB of addressable T1 FAMILY FEATURE LIST memory space Up to 1.5 GHz with 64-bit ISA support Hybrid 32-bit mode to support Two or four e5500 single-threaded Three levels of instructions: User, supervisor, hypervisor cores built on Power Architecture legacy software and seamless Hybrid 32-bit mode to support legacy software and technology transition to 64-bit architecture transition to a 64-bit architecture CoreNet platform cache 256 KB shared platform cache VIRTUALIZATION CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation The T1 family includes support for amongst CoreNet endpoints Hierarchical interconnect fabric hardware-assisted virtualization. The QMAN fabric supporting packet-level queue management and quality of service e5500 core offers an extra core privilege 64-bit DDR3L/4 SDRAM memory level (hypervisor). Virtualization software Up to 1600 MT/s controller with ECC support for the T1 family includes kernel- Packet parsing, classification and distribution based virtual machine (KVM), Linux Queue management for scheduling, packet sequencing OS containers, NXP hypervisor and and congestion management DPAA incorporating acceleration for the following functions commercial virtualization software from Hardware buffer management for buffer allocation and de-allocation Green Hills Software and Enea . Cryptography acceleration (SEC 5.x) Eight lanes at up to 5 Gb/s SerDes DATA PATH ACCELERATION Supports SGMII, QSGMII, PCI Express and SATA ARCHITECTURE (DPAA) 8-port Gigabit Ethernet switch (available with T1040 and T1020 only) Ethernet interfaces The T1 family integrates the QorIQ Up to 5x 1 Gb/s Ethernet MACs DPAA, an innovative multicore QUICC Engine module Support for legacy protocols TDM, HDLC, UART and ISDN infrastructure for scheduling work to High-speed peripheral interfaces Four PCI Express 2.0 controllers cores (physical and virtual), hardware accelerators and network interfaces. Two serial ATA (SATA 2.0) controllers Two High-Speed USB 2.0 controllers with integrated PHYs Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface Additional peripheral interfaces DPAA HARDWARE ACCELERATORS 2 Two I C controllers Four UARTS 13 Gb/s classify, parse Frame manager (FMAN) and distribute Integrated flash controller supporting NAND and NOR flash memory Buffer manager (BMAN) 64 buffer pools DMA Dual four channel 24 Queue manager (QMAN) Up to 2 queues Support for hardware virtualization Extra privileged level for hypervisor support and partitioning enforcement Security (SEC) 5 Gb/s: 3DES, AES QorIQ trust architecture Secure boot, secure debug, tamper detection, volatile key storage PCle PCle PCle PCle SAT A 2.0 SAT A 2.0 TDM/HDLC TDM/HDLC