QorIQ Communications Platforms T Series QorIQ T1040/20 and T1042/22 communication processors Overview e5500 Core DPAA Hardware Accelerators The QorIQ T1 family of communications The T1 family is based on the 64-bit e5500 Frame manager (FMAN) 13 Gb/s classify, parse processors combines up to four 64-bit cores, Power Architecture core, which uses a seven- and distribute Buffer manager (BMAN) 64 buffer pools built on Power Architecture technology, with stage pipeline for low latency response to 24 Queue manager (QMAN) Up to 2 queues high-performance Data Path Acceleration unpredictable code execution paths, boosting Security (SEC) 5 Gb/s: 3DES, AES Architecture (DPAA) and network peripheral single-threaded performance. bus interfaces required for networking and e5500 Core Features telecommunications. This scalable, pin- Data Path Acceleration compatible family also features the industrys Supports up to 1.4 GHz core frequencies Architecture (DPAA) first 64-bit embedded processor with an Tightly coupled low latency cache hierarchy integrated Gigabit Ethernet switch, the T1040 The T1 family integrates the QorIQ DPAA, 32 KB I/D (L1), 256 KB L2 per core (and dual-core T1020), which simplifies an innovative multicore infrastructure for hardware design, reduces power and overall scheduling work to cores (physical and virtual), Up to 256 KB of shared platform cache (L3) system cost. hardware accelerators and network interfaces. 3.0 DMIPS/MHz per core The FMAN, a primary element of the DPAA, Target Markets Up to 64 GB of addressable parses headers from incoming packets, then and Applications memory space classifies and selects data buffers with optional policing and congestion management. The The T1 family is ideally suited for use in Hybrid 32-bit mode to support legacy FMAN passes its work to the QMAN which mixed control and data plane applications software and seamless transition to assigns it to cores or accelerators with a such as fixed routers, switches, Internet 64-bit architecture multilevel scheduling hierarchy. access devices, firewall and other packet filtering applications, as well as general- Virtualization Gigabit Ethernet Switch purpose embedded computing. Its high level The T1 family includes support for hardware- of integration offers significant performance The T1040 and T1020 processors include assisted virtualization. The e5500 core offers benefits and greatly helps to simplify board an integrated gigabit Ethernet switch that an extra core privilege level (hypervisor). design. supports wire-speed switching for all packet Virtualization software for the T1 family includes sizes. Other features include VLAN, QoS Enterprise equipment: Fixed routers, kernel-based virtual machine (KVM), Linux processing and ACLs. Ethernet switches, UTM equipment OS containers, Freescale hypervisor and commercial virtualization software from Green Service provider: Edge routers, Hills Software and Enea . mobile backhaul Aerospace, defense and government: Ruggedized network appliances QorIQ T1040/20 and T1042/22 Communications Processors QorIQ T1040/20 and T1042/22 Communications Processors Industrial computing: Single board Power Architecture computers, factory automation, 256 KB e5500 Backside smart grid L2 Cache 32/64-bit 32 KB 32 KB 256 KB DDR3L/4 Platform Cache D Cache I Cache Memory Controller Security Fuse Processor CoreNet Coherency Fabric Peripheral Security Monitor Access PAMU PAMU PAMU PAMU Mgmt. Unit 16-bit IFC Real-Time Debug Power Management QUICC Parse, Classify, Distribute T1040: Engine Security 5.4 Queue 2x DMA, SDXC/eMMC Watchpoint 1 GbE 1 GbE (XoR CRC) Mgr. 1 GbE T1042: Cross Trigger 2x DUART 1 GbE 1 GbE 4x DMA T1042/T1022 Only 2 4x I C Perf. Trace Pattern 8 Port Switch Monitor T1040/ Buffer SPI, GPIO 1 GbE 1 GbE 1 GbE 1 GbE Match T1020 Mgr. Aurora Engine 2.0 1 GbE 1 GbE 1 GbE 1 GbE Only 2x USB 2.0 w/PHY DIU 8-Lane 5 GHz SerDes Core Complex (CPU, L2, L3 Cache) Basic Peripherals and Interconnect Accelerators and Memory Control Networking Elements PCle PCle PCle PCle SATA 2.0 SATA 2.0 TDM/HDLC TDM/HDLC T1 Family Comparison T1020 T1022 T1040 T1042 T2081 CPU 2 e5500 2 e5500 4 e5500 4 e5500 4 e6500 (dual threaded) 12001400 MHz 12001400 MHz 12001400 MHz 12001400 MHz 15001800 MHz DDR I/F 1x DDR3L/4 to 1600 MT/s 1x DDR3L/4 to 1600 MT/s 1x DDR3L/4 to 1600 MT/s 1x DDR3L/4 to 1600 MT/s 1x DDR3/3L to 22133 MT/s 10/100/1000 Ethernet 8-port GbE switch 5x 1 GbE 8-port GbE switch 5x 1 GbE 2x 1/10 GbE (with IEEE 1588v2) + 4x 1 GbE + 4x 1 GbE + 6x 1 GbE SerDes Eight lanes (5 GHz) Eight lanes (5 GHz) Eight lanes (5 GHz) Eight lanes (5 GHz) Eight lanes (10 GHz) Package Pin compatible System Peripherals and Networking T1 Family Feature List For networking, the FMAN supports up to five Up to 1.4 GHz with 64-bit ISA support 1 Gb/s MAC controllers that connect to PHYs, Two or four e5500 single-threaded Three levels of instructions: User, supervisor, hypervisor cores built on Power Architecture switches and backplanes over RGMII and SGMII. Hybrid 32-bit mode to support legacy software and transition technology to a 64-bit architecture The T1040 and T1020 processors also include an CoreNet platform cache 256 KB shared platform cache integrated 8-port Gigabit Ethernet switch, which supports QSGMII or SGMII interfaces. High-speed CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation system expansion is supported through three PCI amongst CoreNet endpoints Hierarchical interconnect fabric Express V2.0 controllers that support a variety QMAN fabric supporting packet-level queue management and quality of service of lane widths. Other peripherals include SATA, 2 SD/MMC, I C, UART, SPI, NOR/NAND controller, 64-bit DDR3L/4 SDRAM memory Up to 1600 MT/s controller with ECC support GPIO and a 1600 MT/s DDR3L/4 controller. Packet parsing, classification and distribution Software and Tool Support Queue management for scheduling, packet sequencing and congestion management DPAA incorporating acceleration Freescale and our partner network deliver a for the following functions Hardware buffer management for buffer allocation and wide range of tools, run-time software, reference de-allocation Cryptography acceleration (SEC 5.x) solutions and services to accelerate your designs. Eight lanes at up to 5 Gb/s SerDes QorIQ reference design boards Supports SGMII, QSGMII, PCI Express and SATA CodeWarrior Development Studio for Power 8-port Gigabit Ethernet switch (available with T1040 and T1020 only) Ethernet interfaces Architecture Up to 5x 1 Gb/s Ethernet MACs Freescale Linux SDK QUICC Engine module Support for legacy protocols TDM, HDLC, UART and ISDN Reference Platforms High-speed peripheral interfaces Four PCI Express 2.0 controllers Two serial ATA (SATA 2.0) controllers Enterprise WLAN Access Point Two High-Speed USB 2.0 controllers with integrated PHYs Enhanced secure digital host controller (SD/MMC/eMMC) VortiQa Application Software Enhanced serial peripheral interface Additional peripheral interfaces 2 AISApplication Identification Software Two I C controllers Four UARTS Enterprise Software for Networking Integrated flash controller supporting NAND and NOR flash memory ONSOpen Network Switch Software DMA Dual four channel ONDOpen Network Director Software Support for hardware virtualization Extra privileged level for hypervisor support and partitioning enforcement Professional Services & Support Secure boot, secure debug, tamper detection, volatile key QorIQ trust architecture Commercial Services storage Linux SDK Support Package Reference Design Software (RDS) Support Package Third Party Software and Tools Enea, Green Hills, Mentor Graphics and Wind River For more information, please visit freescale.com/QorIQ Freescale, the Freescale logo and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm Off. CoreNet and QUICC Engine are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. 2012, 2013 Freescale Semiconductor, Inc. Document Number: T1FAMILYFS REV 1