T1024NSE7PQA NXP

Document Number T1024, T1014 Freescale Semiconductor Rev. 0, 07/2015 Data Sheet: Technical Data T1024, T1014 QorIQ T1024, T1014 Data Sheet Features Additional peripheral interfaces Two high-speed USB 2.0 controllers with integrated e5500 cores built on Power Architecture technology, PHY T1024 has two cores and T1014 has a single core Enhanced secure digital host controller with support Each core has a private 256KB L2 cache for high capacity memory card(SD/eSDHC/eMMC) 256 KB shared L3 CoreNet platform cache (CPC) Enhanced Serial peripheral interface (eSPI) Four I2C controllers Hierarchical interconnect fabric Two DUARTs CoreNet Coherency manager supporting coherent Integrated flash controller supporting NAND and and non-coherent transactions with prioritization and NOR flash bandwidth allocation amongst CoreNet end-points Display interface unit (DIU) with 12-bit dual data 150Gbps coherent read bandwidth rate One 32-/64-bit DDR3L/DDR4 SDRAM memory Multicore programmable interrupt controller (MPIC) controllers QUICC Engine block ECC and interleaving support 32-bit RISC controller for flexible support of the Data Path Acceleration Architecture (DPAA) communications peripherals incorporating acceleration for the following functions: Serial DMA channel for receive and transmit on all Packet parsing, classification, and distribution serial channels Queue management for scheduling, packet Two universal communication controllers, sequencing, and congestion management supporting TDM, HDLC and UART Hardware buffer management for buffer allocation 780 FC-PBGA package, 23 mm x 23 mm and de-allocation Cryptography Acceleration IEEE Std 1588 support Parallel Ethernet interfaces Up to two RGMII interface Four SerDes lanes for high-speed peripheral interfaces Three PCI Express 2.0 controllers One Serial ATA (SATA 3Gb/s) controller Up to three SGMII interface supporting 1000 Mbps Up to three SGMII interface supporting 2500Mbps Up to one XFI (10GbE) interface Up to one QSGMII interface Supports 1000Base-KX Supports 10GBase-KR 20142015 Freescale Semiconductor, Inc.Table of Contents 1 Overview.............................................................................................. 3 3.18 I2C interface.............................................................................. 130 2 Pin assignments.................................................................................... 4 3.19 GPIO interface...........................................................................133 2.1 780 ball layout diagrams........................................................... 4 3.20 Display interface unit................................................................ 136 2.2 Pinout list...................................................................................10 3.21 High-speed serial interfaces (HSSI).......................................... 137 3 Electrical characteristics.......................................................................43 4 Hardware design considerations...........................................................161 3.1 Overall DC electrical characteristics.........................................43 4.1 System clocking........................................................................ 161 3.2 Power sequencing......................................................................50 4.2 Power supply design..................................................................170 3.3 Power-down requirements.........................................................54 4.3 Decoupling recommendations...................................................175 3.4 Power-on ramp rate................................................................... 54 4.4 SerDes block power supply decoupling recommendations.......176 3.5 Power characteristics.................................................................54 4.5 Connection recommendations................................................... 176 3.6 Input clocks............................................................................... 59 4.6 Thermal......................................................................................187 3.7 RESET initialization..................................................................65 4.7 Recommended thermal model...................................................188 3.8 DDR4 and DDR3L SDRAM controller.................................... 66 4.8 Temperature diode.....................................................................188 3.9 eSPI interface.............................................................................73 4.9 Thermal management information............................................ 189 3.10 DUART interface...................................................................... 76 5 Package information.............................................................................191 3.11 Ethernet interface, Ethernet management interface, IEEE Std 5.1 Package parameters for the FC-PBGA......................................191 1588........................................................................................... 78 5.2 Mechanical dimensions of the FC-PBGA................................. 191 3.12 QUICC Engine Specifications...................................................102 6 Security fuse processor.........................................................................193 3.13 USB interface............................................................................ 108 7 Ordering information............................................................................193 3.14 Integrated flash controller..........................................................109 7.1 Part numbering nomenclature....................................................193 3.15 Enhanced secure digital host controller (eSDHC).....................117 7.2 Part marking.............................................................................. 194 3.16 Multicore programmable interrupt controller (MPIC).............. 125 8 Revision history....................................................................................195 3.17 JTAG controller.........................................................................127 QorIQ T1024, T1014 Data Sheet, Rev. 0, 07/2015 2 Freescale Semiconductor, Inc.