CAV93C56 EEPROM Serial 2-Kb Microwire - Automotive Grade 1 Description www.onsemi.com The CAV93C56 is an EEPROM Serial 2 Kb Microwire Automotive Grade 1 device, which is organized as either 128 registers of 16 bits (ORG pin at V ) or 256 registers of 8 bits (ORG pin at CC GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAV93C56 features sequential read and selftimed SOIC8 TSSOP8 internal write with autoclear. Onchip PowerOn Reset circuitry V SUFFIX Y SUFFIX protects the internal logic against powering up in the wrong state. CASE 751BD CASE 948AL Features Automotive AECQ100 Grade 1 (40C to +125C) Qualified PIN CONFIGURATIONS High Speed Operation: 2 MHz 2.5 V to 5.5 V Supply Voltage Range 1 V CS CC SK NC Selectable x8 or x16 Memory Organization DI ORG Sequential Read DO GND Software Write Protection SOIC (V), TSSOP (Y) (Top View) Powerup Inadvertant Write Protection Low Power CMOS Technology 1,000,000 Program/Erase Cycles PIN FUNCTION 100 Year Data Retention Pin Name Function 8pin SOIC and TSSOP Packages CS Chip Select These Devices are PbFree, Halogen Free/BFR Free and are RoHS SK Clock Input Compliant DI Serial Data Input V CC DO Serial Data Output V Power Supply CC ORG GND Ground CS ORG Memory Organization CAV93C56 DO SK NC No Connection DI GND ORDERING INFORMATION See detailed ordering and shipping information in the package Figure 1. Functional Symbol dimensions section on page 8 of this data sheet. NOTE: When the ORG pin is connected to V , the x16 organization is selected. CC When it is connected to ground, the x8 pin is selected. If the ORG pin is left unconnected, then an internal pullup device will select the x16 organization. Semiconductor Components Industries, LLC, 2013 1 Publication Order Number: April, 2019 Rev. 2 CAV93C56/DCAV93C56 Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Storage Temperature 65 to +150 C Voltage on Any Pin with Respect to Ground (Note 1) 0.5 to +6.5 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The DC input voltage on any pin should not be lower than 0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may CC undershoot to no less than 1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns. CC Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol Parameter Min Units N (Note 3) Endurance 1,000,000 Program / Erase Cycles END T Data Retention 100 Years DR 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100 and JEDEC test methods. 3. Block Mode, V = 5 V, 25C CC Table 3. D.C. OPERATING CHARACTERISTICS (V = +2.5 V to +5.5 V, T =40C to +125C unless otherwise specified.) CC A Symbol Parameter Test Conditions Min Max Units I Power Supply Current (Write) V = 5.0 V 2 mA CC1 CC I Power Supply Current (Read) f = 2 MHz, V = 5.0 V, DO open 500 A CC2 SK CC I Power Supply Current (Standby) V = GND or V , 5 A SB1 IN CC (x8 Mode) CS = GND ORG = GND I Power Supply Current (Standby) V = GND or V , 3 A SB2 IN CC (x16 Mode) CS = GND ORG = Float or V CC I Input Leakage Current V = GND to V 2 A LI IN CC I Output Leakage Current V = GND to V , CS = GND 2 A LO OUT CC V Input Low Voltage 4.5 V V < 5.5 V 0.1 0.8 V IL1 CC V Input High Voltage 4.5 V V < 5.5 V 2 V + 1 V IH1 CC CC V Input Low Voltage 2.5 V V < 4.5 V 0 V x 0.2 V IL2 CC CC V Input High Voltage 2.5 V V < 4.5 V V x 0.7 V + 1 V IH2 CC CC CC V Output Low Voltage 4.5 V V < 5.5 V, I = 3 mA 0.4 V OL1 CC OL V Output High Voltage 4.5 V V < 5.5 V, I = 400 A 2.4 V OH1 CC OH V Output Low Voltage 2.5 V V < 4.5 V, I = 1 mA 0.2 V OL2 CC OL V Output High Voltage 2.5 V V < 4.5 V, I = 100 A V 0.2 V OH2 CC OH CC Table 4. PIN CAPACITANCE (T = 25C, f = 1 MHz, V = 5 V) A CC Symbol Test Conditions Min Typ Max Units C (Note 4) Output Capacitance (DO) V = 0 V 5 pF OUT OUT C (Note 4) Input Capacitance (CS, SK, DI, ORG) V = 0 V 5 pF IN IN 4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100 and JEDEC test methods. www.onsemi.com 2