EVBUM2706/D LC823455 Evaluation Board User s Manual Overview This document describes the hardware board of the LC823455 evaluation kit to help you understand the www.onsemi.com functions and schematics of the board. The block diagrams help you understand large scale schematics. Illustrations EVAL BOARD USERS MANUAL with detailed explanations help you learn the functions, and how to use and operate this board. This document applies to the users of this evaluation board as well as designers who plan to use the LC823455 to custom design a board. Audio I/O Handling Precautions for This Board Dedicated DAMP output terminal for SE and BTL This board includes many ESD sensitive electronic Dedicated DAMP LC LPF for SE and BTL devices. The following items are required to handle this board: HighResolution Audio ready external ADC and DAC Use this board in the ESD Protected Area (EPA). Dedicated Headphone Amplifier for external DAC Remove the ESD bag in the EPA. Volume control for Headphone Amplifier Remove static from your body when using the board. 3.5 mm stereo jacks for analog audio I/O When not in use, store the evaluation board in the ESD 2x Onboard MEMS digital microphones bag. USB 2.0 Interface Do not apply excess or reverse voltage to any terminals on Device and Host available this board. External boost DCDC for Host and OTG operation Features Insertion/Extraction detection Flexible Development and Evaluation Board Header pins to access almost pins of LC823455 Storage Header pins to connect users power supply or PMIC Onboard eMMC and serial flash (selectable) Universal area to add users circuits or connectors 1x microSD slot Connectors to add ARDUINO shield or Pmod module Wireless Connectivity Three Types of Power Supply Input Connectors PCI Express M.2 connector for WiFi/BT module Micro USB connector (for USB buspowered operation) Embedded Artists 1MW (Murata) WiFi/BT M.2 module Industrial standard, 5.5 mm/2.1 mm DC Jack ( EAR00315) JST XH 2-pin connector (for connecting battery) ManMachine Interface Single 5 V Supply Operation by Onboard Regulators 8x Push Switch PMIC for LC823455 2x LED (Red & Green) 1x Character LCD DCDC: 1.0 V/1.1 V/1.8 V, LDO: 1.0 V/1.5 V/1.8 V/3.3 V RTC Power Supply Development and Debug Ports UART with USBserial bridge (micro USB connector) Dedicated Low Iq LDOs, 0.8 V and 1.0 V SWD for Cortex M3 (20pin Box Header) General-purpose 3.3 V DCDC JTAG for LPDSP (20pin Box Header) microSD slot dedicated 2.8 V DCDC WiFi /BT dedicated regulators Boot Mode Setting ARDUINO shield and Pmod dedicated 3.3 V LDO Easy setting by two rotary switches Semiconductor Components Industries, LLC, 2019 1 Publication Order Number: December, 2019 Rev. 0 EVBUM2706/DEVBUM2706/D Clock and the LCD instantaneously. U603 supervises Vdd2 voltage and provides POR (Power On Reset) functions. No external clock source or generator required When U603 detects proper voltage, reset is released. Onboard clock sources: Two types of Vdd2 (1.8 V and 3.3 V) are available on this 24 MHz crystal resonator for PLL source evaluation board. Therefore the detection voltage of POR 32.768 kHz crystal resonator for RTC must be set to the proper Vdd2 voltage. JP603 provides this 32.768 kHz crystal oscillator for WiFi/BT module setting. When changing the Vdd2 voltage via SW101, also remember to change the configuration of JP603. Vdd2 and Battery Connectivity JP603 are set to 1.8 V by default. cell LiIon Battery available CAUTION: The configuration of SW101 and JP603 must Onboard charger IC be changed only when powered off. When you change these Battery voltage monitor function settings, unplug power supply cable from this board or turn off the power supply. Detailed Explanation for Function Block in This Board Refer to Figure 1Figure 6 and schematics for a better Boot Mode understanding of the following explanation. The circuit to set the boot mode of LC823455 consists of two 4pole rotary type switches and resistors to fix the logic Battery Monitor level. To change the boot mode, set SW611 and SW612 to An integrated ADC monitors VBAT voltage. An external your desired setting then, push SW610 to reset and reboot resistor divider circuit scales the fullscale level of ADC and LC823455. After resetting, LC823455 operates in the new input voltage. mode setting of SW611 and SW612. ManMachine Interface A 2.5 mm standard, flatblade screwdriver (not supplied Eight push switches, two LEDs (red, green), and the LCD in the evaluation kit) is required to change the setting of character display provide manmachine interface function these rotary switches. to the user. Software running on the LC823455 assign The following tables show the relationship between the functions for these switches, LEDs, and the LCD. The red SW611 and SW612 settings and boot mode (Table1, LED is not softwareconfigurable and shows the operating Table 2, and Table 3). status of LC823455 and is connected to pin EXTINT2F of the LC823455. For more information, refer to the LC823455 Table 1. BOOT MODE SETTING SWITCH AND datasheet description of EXTINT2F. IPL MODE USB 2.0 Interface SW611 SW612 Usually, this USB port operates as Device. BMODE1 BMODE0 IPL Mode LC823455 can be operated as USB Host by setting of 0 0 SPI Boot (USB) software and U3. In this case, set JP21 to Host. JP21 is set to Device by default. Refer to related LC823455 0 1 SPI All Erase documents for details about operating as USB Host. 0 2 User Area Boot (SD) The USB 2.0 port functions as a power supply input when 0 3 External ROM Boot configured as USB Device. When the port connects to USB Host equipment, such as a PC, other power supplies are 1 0 QSPI Boot (USB) not required. 1 1 HiZ VBUS in this port connects to pin KEYINT1 of 1 2 QSPI All Erase LC823455 via a resistor divider. RTC functions of 1 3 QSPI Boot (SD) LC823455 provide insertion and extraction detection of the USB connector. 2 0 User Boot (USB) Development and Debug Port 2 1 User Area Delete The Development and Debug Port is used for software 2 2 SDCH0 All Erase development and debugging. CN601 is an SWD interface 2 3 User Boot (USB) connected to the builtin CortexM3 to LC823455. CN602 is a JTAG interface linked to the builtin LPDSP. CN1 is 3 0 Physical Boot (SD) connected to UART0 of LC823455 via USB to serial UART 3 1 SPI Boot (SD) IC:FT232, which is industry standard. 3 2 Partition Delete RESET/POR 3 3 Physical Boot (USB) A reset circuit connected to U1 (LC823455), U301 (I/O Expander), and LCD601 (LCD Module) can reset these ICs www.onsemi.com 2