Half Bridge Gate Driver (Isolated High & Non-Isolated Low) NCD57200 The NCD57200 is a high voltage gate driver with one nonisolated low side gate driver and one galvanically isolated high or low side gate www.onsemi.com driver. It can directly drive two IGBTs in a half bridge configuration. Isolated high side driver can be powered with an isolated power supply or with Bootstrap technique from the low side power supply. The galvanic isolation for the high side gate driver guarantees 8 reliable switching in high power applications for IGBTs that operate 1 up to 800 V, at high dv/dt. The optimized output stages provide a mean SOIC8 NB of reducing IGBT losses. Its features include two independent inputs CASE 75107 with deadtime and interlock, accurate asymmetric UVLOs, and short and matched propagation delays. The NCD57200 operates with its V /V up to 20 V. DD BS MARKING DIAGRAM Features 8 High Peak Output Current (+1.9 A/2.3 A) NCD57200 Low Output Voltage Drop for Enhanced IGBT Conduction ALYWX Floating Channel for Bootstrap Operation up to +800 V CMTI up to 100 kV/ s 1 Reliable Operation for V Negative Swing to 800 V S VDD & VBS Supply Range up to 20 V NCD57200 = Specific Device Code A = Assembly Location 3.3 V, 5 V, and 15 V Logic Input L = Wafer Lot Asymmetric Under Voltage Lockout Thresholds for High Side and Y = Year Low Side W = Work Week = PbFree Package Matched Propagation Delay 90 ns Builtin 20 ns Minimum Pulse Width Filter (or Input Noise Filter) Builtin 340 ns DeadTime and High and Low Inputs Interlock PIN CONNECTIONS NonInverting Output Signal V V DD B This Device is PbFree, Halogen Free/BFR Free and is RoHS Compliant HIN HO Typical Applications LIN V S Fans, Pumps Home Appliances GND LO Consumer Electronics General Purpose Half Bridge Applications ORDERING INFORMATION See detailed ordering and shipping information on page 15 of this data sheet. Semiconductor Components Industries, LLC, 2019 1 Publication Order Number: July, 2020 Rev. 1 NCD57200/DNCD57200 V B V DD V DD UVLO2 HO Minimum Input Output HIN Pulse Logic Logic Width V S Deadtime and Interlock V DD UVLO1 LO Minimum Matching LIN Pulse Delay Width GND Figure 1. Simplified Block Diagram V DD V V DD B HIN HO V LIN S GND LO Figure 2. Simplified Application Schematics www.onsemi.com 2