LDO Regulator, 3 A, High Accuracy (1%), Low Noise (4.3 V ), Low Dropout RMS (70 mV) NCP59763 www.onsemi.com The NCP59763 is a 3 A capable, low noise (4.3 V ), ultra low RMS dropout (70 mV max. at 3 A), fast load transient response linear regulator (LDO) equipped with an NMOS pass transistor without the need of external bias voltage. The device output voltage is adjustable from 0.5 V to 2.0 V through the use of an external resistor divider and also available in fixed output versions. The combination of high output current capability, ultra high PSRR 1 DFN10, 3x3 across a wide frequency range and low noise makes this LDO ideal for CASE 506EH powering noise sensitive high speed communication devices. Power sequencing application flexibility through enable pin, a user programmable softstart and a user programmable delayed power good MARKING DIAGRAM circuit. Very low dropout voltage (70 mV) and high output voltage accuracy (1%) enables low input voltage and higher power efficiency. 59763 These set of features makes NCP59763 LDO an ideal solution for Pxxxy powering analog, digital and mixed signal high current demanding ALYW circuits like analogtodigital converters (ADCs), digitaltoanalog converters (DACs), high performance serializers and deserializers 59763P = Specific Device Code (SerDes), application specific integrated circuits (ASICs), field xxx = Output Voltage Version programmable gate arrays (FPGAs), digital signal processors (DSPs). y = Output Discharge Version A = Assembly Location Features L = Wafer Lot Y = Year High Output Current 3 A W = Work Week High Accuracy 1% Including Line/Load Regulation and = PbFree Package Temperature Variation (Note: Microdot may be in either location) Input Voltage Range: 1.1 V to 3.6 V Adjustable and Fixed Output Voltage Options Available Adj Voltage Range: 0.5 V to 2.0 V ORDERING INFORMATION See detailed ordering and shipping information on page 33 of Fixed: 0.5 V, 0.8 V, 1.0 V, 1.2 V this data sheet. Dropout Voltage: 70 mV Typ. at 3 A Very Low Output Voltage Noise: 4.3 V Typ. (10 Hz 100 kHz) RMS Excellent Transient Response (20 mV Undershoot at 0.13 A Step) Typical Applications High PSRR: 70 dB High Speed Analog VCO, ADC, DAC Programmable Soft Start FPGAs, DSPs, SerDes Open Drain Power Good Output with Programmable Delay Imaging Sensors and ASICs DFN10 3.0 x 3.0 mm with Enhanced Thermal Performance Communications, Test, Measurement PbFree, Halogen Free/BFR Free and are RoHS Compliant C FF NCP59763 1.1V3.6V R 0.5V2.0V / 3A ADJ1 10nF IN IN OUT OUT C C IN OUT EN 10uF 47uF FB CF R PG C CF R 100k ADJ2 10nF NR/ SS C DELAY NR/SS PG PG GND 100nF C DELAY 2.2nF Figure 1. Typical Application Schematic Semiconductor Components Industries, LLC, 2019 1 Publication Order Number: June, 2021 Rev. 4 NCP59763/DNCP59763 Current OUT IN Limit Charge Pump Output CF discharge R NR Progr. Voltage Reference EA I SS FB NR/SS PG NR/SS Discharge 90% of UVLO V REF I DELAY 1.0V EN EN DELAY Logic & 0.8V 0.8V Delays PG Thermal Shutdown Figure 2. Simplified Schematic Block Diagram 1 10 IN OUT 2 9 IN OUT 3 8 CF FB GND 4 7 PG NR/SS 5 6 DELAY EN (Top View) Figure 3. Pin Assignment Table 1. PIN FUNCTION DESCRIPTION Pin Name Description 1,2 IN Input voltage supply pins. 3 CF Internal supply filtering capacitor. 4 PG PowerGood (PG) is an opendrain, activehigh output that indicates the status of V . When V OUT OUT exceeds the PG trip threshold, the PG pin goes into a highimpedance state. When V is below this OUT threshold the pin is driven to a lowimpedance state. A pullup resistor from 10 k to 1 M should be connected from this pin to a supply up to 3.6 V. The supply can be higher than the input voltage. Alter- natively, the PG pin can be left floating if output monitoring is not necessary. 5 DELAY This pin is intended for adjusting the delay for signaling V is OK according to the user application OUT needs. Capacitor connected from this pin to GND with capacitance of 2.2 nF corresponds to 1 ms delay. The maximum delay applicable is 100 ms. If delay not necessary the DELAY pin can be left floating. 6 EN Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shut- down mode. This pin must not be left floating. 7 NR/SS Noisereduction and softstart pin. Connecting an external capacitor between this pin and ground reduces reference voltage noise and also enables the soft start function. Although not required, a 10 nF or larger capacitor is recommended to be connected from NR/SS to GND (as close to the pin as possible) to maximize ac performance. 8 FB This pin is the feedback connection to the center tap of an external resistor divider network that sets the output voltage. Connect this pin to OUT pin directly when output voltage adjustment is not needed (then the output voltage V will be equal to the nominal voltage V ). OUT NOM 9,10 OUT Regulated output voltage. It is recommended that the output capacitor effective capacitance 47 F. TAB GND Ground and thermal pad. www.onsemi.com 2