DATA SHEET www.onsemi.com LDO Regulator, 300 mA, MARKING DIAGRAMS Low Dropout Voltage, 5 Ultra Low Noise, High PSRR TSOP5 XXXAYW 5 CASE 483 with Power Good 1 1 NCV8164 WDFNW6 2x2, 0.65P XXM CASE 511DW The NCV8164 is a 300 mA LDO, next generation of high PSRR, ultralow noise and low dropout regulators with Power Good open collector output. Designed to meet the requirements of RF and 1 sensitive analog circuits, the NCV8164 device provides ultralow DFNW8 3x3, 0.65P XXX noise, high PSRR and low quiescent current. The device also offer CASE 507AD ALYW excellent load/line transients. The NCV8164 is designed to work with 1 a 1 F input and a 1 F output ceramic capacitor. It is available in XXX = Specific Device Code industry standard TSOP5, WDFNW6 0.65P, 2 mm x 2 mm and A = Assembly Location DFNW8 0.65P, 3 mm x 3 mm. L = Wafer Lot M = Month Code Features Y = Year Operating Input Voltage Range: 1.6 V to 5.5 V W = Work Week = PbFree Package Available in Fixed Voltage Option: 1.2 V to 5.0 V (Note: Microdot may be in either location) Adjustable Version Reference Voltage: 1.2 V 2% Accuracy Over Load and Temperature PIN CONNECTONS Ultra Low Quiescent Current Typ. 30 A Standby Current: Typ. 0.1 A Very Low Dropout: 110 mV at 300 mA for 3.3 V Variant Ultra High PSRR: Typ. 85 dB at 10 mA, f = 1 kHz Ultra Low Noise: 9 V (Fixed Version) RMS Stable with a 1 F Small Case Size Ceramic Capacitors Available in TSOP5 3 mm x 1.5 mm x 1 mm CASE 483 WDFNW6 2 mm x 2 mm x 0.75 mm CASE 511DW DFNW8 3 mm x 3 mm x 0.9 mm CASE 507AD NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements AECQ100 Qualified and PPAP Capable These Devices are PbFree, Halogen Free/BFR Free and are RoHS Compliant Typical Applications ORDERING INFORMATION Communication Systems See detailed ordering, marking and shipping information on InVehicle Networking page 10 of this data sheet. Telematics, Infotainment and Clusters General Purpose Automotive V IN IN OUT NCV8164 C C OUT IN 1 F 1 F EN GND PD Ceramic Ceramic ON OFF Figure 1. Typical Application Schematics Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: September, 2021 Rev. 2 NCV8164/DNCV8164 PIN FUNCTION DESCRIPTION Pin No. Pin No. Pin No. Pin Description TSOP5 WDFNW6 DFNW8 Name 1 6 8 IN Input voltage supply pin 5 1 1 OUT Regulated output voltage. The output should be bypassed with small 1 F ceramic capacitor 3 4 7 EN Chip enable: Applying V < 0.2 V disables the regulator, Pulling V > 0.7 V EN EN enables the LDO 4 / 3 3 PG Power Good, open collector. Use 10 k to 100 k pullup resistor connected to output or input voltage 2 5 6 GND Common ground connection / 4 2 2 ADJ Adjustable output feedback pin (for adjustable version only) 2 2 SNS Sense feedback pin. Must be connected to OUT pin on PCB (for fixed versions only) 4, 5 N/C Not connected, pin can be tied to ground plane for better power dissipation EPAD EPAD EPAD Expose pad should be tied to ground plane for better power dissipation ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit Input Voltage (Note 1) V 0.3 to 6 V IN Output Voltage V 0.3 to V +0.3, max. 6 V OUT IN Chip Enable Input V 0.3 to 6 V CE Power Good Voltage V 0.3 to 6 V PG Power Good Current I 30 mA PG Output Short Circuit Duration t unlimited s SC Maximum Junction Temperature T 150 C J Storage Temperature T 55 to 150 C STG ESD Capability, Human Body Model (Note 2) ESD 2000 V HBM ESD Capability, Charged Device Model (Note 2) ESD 1000 V CDM Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AECQ100002 (EIA/JESD22A114) ESD Charged Device Model tested per EIA/JESD22C101, Field Induced Charge Model www.onsemi.com 2