2 EEPROM Serial 512-Kb I C - Automotive Grade 1 in Wettable Flank UDFN Package NV24C512MUW www.onsemi.com Description 2 The NV24C512MUW is a EEPROM Serial 512Kb I C, internally organized as 65,536 words of 8 bits each. 1 It features a 128byte page write buffer and supports the Standard 2 UDFN8 (100 kHz), Fast (400 kHz) and FastPlus (1 MHz) I C protocol. (WETTABLE FLANK) Write operations can be inhibited by taking the WP pin High (this MUW3 SUFFIX protects the entire memory). CASE 517DH External address pins make it possible to address up to eight NV24C512MUW devices on the same bus. OnChip ECC (Error Correction Code) makes the device suitable MARKING DIAGRAM for high reliability applications. 1 C9W Features AWLYW Automotive AECQ100 Grade 1 (40C to +125C) Qualified 2 Supports Standard, Fast and FastPlus I C Protocol C9W= Specific Device Code 2.5 V to 5.5 V Supply Voltage Range A = Assembly Site WL = Wafer Lot Number 128Byte Page Write Buffer YW = Assembly Start Week Hardware Write Protection for Entire Memory = PbFree Package 2 Schmitt Triggers and Noise Suppression Filters on I C Bus Inputs (SCL and SDA) PIN CONFIGURATION Low Power CMOS Technology 1,000,000 Program/Erase Cycles A V 0 CC 100 Year Data Retention A WP 1 8lead SOIC, TSSOP, UDFN and 8ball WLCSP Packages A SCL 2 These Devices are PbFree, Halogen Free/BFR Free and are RoHS V SDA SS Compliant UDFN8 V CC PIN FUNCTION Pin Name Function SCL A , A , A Device Address 0 1 2 SDA Serial Data NV24C512 SDA A , A , A 2 1 0 SCL Serial Clock WP WP Write Protect V Power Supply CC V Ground SS V SS Figure 1. Functional Symbol ORDERING INFORMATION See detailed ordering and shipping information on page 9 of this data sheet. Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: July, 2020 Rev. 3 NV24C512MUW/DNV24C512MUW Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Storage Temperature 65 to +150 C Voltage on any Pin with Respect to Ground (Note 1) 0.5 to +6.5 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The DC input voltage on any pin should not be lower than 0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may CC undershoot to no less than 1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns. CC Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol Parameter Min Units N (Notes 3, 4) Endurance 1,000,000 Program/Erase Cycles END T Data Retention 100 Years DR 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100 and JEDEC test methods. 3. Page Mode, V = 5 V, 25C. CC 4. The device uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte has to be written, 4 bytes (including the ECC bits) are re-programmed. It is recommended to write by multiple of 4 bytes in order to benefit from the maximum number of write cycles. Table 3. D.C. OPERATING CHARACTERISTICS V = 2.5 V to 5.5 V, T = 40C to +125C, unless otherwise specified. CC A Symbol Parameter Test Conditions Min Max Units I Read Current Read, f = 400 kHz/1 MHz 1 mA CCR SCL I Write Current V = 5.5 V 2.5 mA CCW CC I Standby Current All I/O Pins at GND or V T = 40C to +125C 5 A SB CC A I I/O Pin Leakage Pin at GND or V T = 40C to +125C 2 A L CC A V Input Low Voltage 0.5 0.3 V V IL1 CC V Input High Voltage 0.7 V V + 0.5 V IH1 CC CC V Output Low Voltage I = 3.0 mA 0.4 V OL1 OL Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. Table 4. PIN IMPEDANCE CHARACTERISTICS V = 2.5 V to 5.5 V, T = 40C to +125C, unless otherwise specified. CC A Symbol Parameter Conditions Max Units C (Note 5) SDA I/O Pin Capacitance V = 0 V 8 pF IN IN C (Note 5) Input Capacitance (other pins) V = 0 V 6 pF IN IN I , I (Note 6) WP Input Current, Address Input V < V , V = 5.5 V 75 A WP A IN IH CC Current (A , A , A ) 0 1 2 V < V , V = 3.3 V 50 IN IH CC V > V 2 IN IH 5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100 and JEDEC test methods. 6. When not driven, the WP, A , A , A pins are pulled down to GND internally. For improved noise immunity, the internal pulldown is relatively 0 1 2 strong therefore the external driver must be able to supply the pulldown current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V ), the strong pulldown reverts to a weak current source. CC www.onsemi.com 2