Version 1.3 2010
Features
PEX 8606 General Features
o 6-lane PCI Express switch
PEX 8606
- Integrated 5.0 GT/s SerDes
o Up to 6 configurable ports
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o 15 x 15mm , 196-ball PBGA
o Typical Power: 1.34 Watts
PEX 8606 Key Features
PCIe Gen2, 5.0 GT/s 6-lane 6-port PCI Express Switch
o Standards Compliant
- PCI Express Base Specification r2.0
The ExpressLane PEX 8606 device offers PCI Express switching capability
(Backwards compatible with PCIe
r1.0a/1.1) enabling users to add scalable high bandwidth non-blocking interconnection to a
- PCI Power Management Spec r1.2
wide variety of applications including communications platforms, control plane
- Microsoft Vista Compliant
applications and embedded systems. The PEX 8606 is well suited for fan-out,
- Supports Access Control Services
aggregation, peer-to-peer, and intelligent I/O module applications.
- Dynamic link-width control
- Dynamic SerDes Speed Control
Low Packet Latency & High Performance
o High Performance
The PEX 8606 architecture supports packet cut-thru with a maximum latency of
- Non-blocking internal architecture
190ns in x1 to x1 configuration. This, combined with large packet memory and
- Full line rate on all ports
non-blocking internal switch architecture, provides full line rate on all ports for low-
- Cut-Thru latency: 190ns
latency applications such as communications and embedded. The low latency
- 2KB max payload size
- Read Pacing enables applications to achieve high throughput and performance. In addition to low
(intelligent bandwidth allocation)
latency, the device supports a max payload size of 2048 bytes, enabling the user to
- Dual Cast
achieve even higher throughout.
o Dual-Host & Fail-Over Support
- Configurable Non-Transparent port
Data Integrity
- Moveable upstream port
- Crosslink port capability The PEX 8606 provides end-to-end CRC protection (ECRC) and Poison bit support
o Flexible Configuration to enable designs that require guaranteed error-free packets. PLX also supports
- 6 flexible & configurable ports
data path parity and memory (RAM) error correction as packets pass through the
(x1 or x2)
switch.
- Configurable with strapping pins,
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EEPROM, I C, or Host software
Dual-Host and Fail-Over Support
- Lane and polarity reversal
o PCI Express Power Management
The PEX 8606 supports full non-transparent bridging (NTB) functionality to allow
- Link power management states: L0, L0s,
implementation of multi-host systems and intelligent I/O modules in applications
L1, L2/L3 Ready, and L3
which require redundancy support such as communications, storage, and servers.
- Device states: D0 and D3
hot
o Spread Spectrum Clock Isolation Non-transparent bridges allow systems to isolate host memory domains by
- Dual clock domain
presenting the processor subsystem as an endpoint rather than another memory
o Quality of Service (QoS)
system. Base address registers are used to translate addresses; doorbell registers are
- Two Virtual Channels (VC) per port
used to send interrupts between the address domains; and scratchpad registers are
- Eight Traffic Classes per port
accessible from both address domains to allow inter-processor communication.
- Weighted Round-Robin Port & VC
Arbitration
Interoperability
o Reliability, Availability, Serviceability
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- All ports Hot-Plug capable thru I C
The PEX 8606 is designed to be fully compliant with the PCI Express Base
(Hot-Plug Controller on every port)
Specification r2.0 and is backwards compatible to PCI Express Base Specification
- ECRC & Poison bit support
r1.1 and r1.0a. Additionally each port supports auto-negotiation, lane reversal and
- Data path protection
polarity reversal. Furthermore, the PEX 8606 is designed for Microsoft Vista
- Memory (RAM) error correction
compliance. All PLX switches undergo thorough interoperability testing in PLXs
- Advanced Error Reporting support
Interoperability Lab and compliance testing at the PCI-SIG plug-fest to ensure
- Port Status bits and GPIO available
- Per port error diagnostics compatibility with PCI Express devices in the market.
- Performance monitoring
(per port payload & header counters)
Device Operation Configuration Flexibility
- JTAG AC/DC boundary scan
The PEX 8606 provides several ways to configure its operations. The device can be
- Fatal Error (FATAL_ERR#) output signal
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configured through strapping pins, I C interface, CPU configuration cycles and/or an
- INTA# output signal
optional serial EEPROM. This allows for easy debug during the development phase
and functional monitoring during the operation phase.
optimization of power and signal strength in a system. The
Flexible Port Configurations
PLX SerDes implementation supports four levels of power
The PEX 8606 supports the port configurations as shown in
off, low, typical, and high. The SerDes block also supports
figure 1 below. The figure shows a 6-port configuration and a
loop-back modes and advanced reporting of error
5-port configuration.
conditions, which enables efficient debug and management of
the entire system.
Port and Virtual Channel (VC) Arbitration
The PEX 8606 switch supports hardware fixed and Weighted
Round-Robin (WRR) Ingress Port Arbitration. This allows
fine tuning of Quality of Service and efficient use of packet
buffers for better system performance. The PEX 8606 also
supports WRR VC arbitration scheme between the two virtual
channels.
Applications
Suitable for fan-out, control plane applications, embedded
systems as well as intelligent I/O and host isolation
applications, PEX 8606 can be configured for a wide variety
Figure 1. Port Configurations
of form factors and applications.
Hot-Plug for High Availability
Fan-Out
Hot-Plug capability allows users to replace hardware modules
The PEX 8606 switch, with its high port count and flexible
and perform maintenance without powering down the system.
configurations, allows user specific tuning to a variety of host-
The PEX 8606 Hot-Plug capability feature makes it suitable
centric as well as peer-to-peer applications.
for High Availability (HA) applications. If the PEX 8606 is
used in an application where one or more of its downstream
ports connect to PCI Express slots, each ports Hot-Plug
Controller can be used to manage the Hot-Plug event of its
associated slot. Every port on the PEX 8606 is equipped with
a Hot-Plug control/status register to support Hot-Plug
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capability through external logic via the I C interface.
Dual Cast
The PEX 8606 supports Dual Cast, a feature which allows for
the copying of data (e.g. packets) from one ingress port to two
egress ports allowing for higher performance in storage,
security, and mirroring applications.
Read Pacing
The Read Pacing feature allows users to throttle the amount of
read requests being made by downstream devices. In the case
Figure 2. Fan-in/out Usage
where a downstream device requests several long reads back-
to-back, the Root Complex gets tied up in serving this
Figure 2 shows a typical fan-out design, where the processor
downstream port. If this port has a narrow link and is therefore
provides a PCI Express link that needs to be fanned into a
slow in receiving these read packets from the Root Complex,
larger number of smaller ports for a variety of I/O functions,
then other downstream ports may become starved thus,
each with different bandwidth requirements.
impacting performance. The Read Pacing feature enhances
In this example, the PEX 8606 would typically have a 1-lane
performances by allowing for the adequate servicing of all
upstream port, and as many as 5 downstream ports. The
downstream devices by intelligent handling of read requests.
downstream ports provide x1 PCI Express connectivity to the
endpoints. With its six ports, the PEX 8606 can provide fan-
SerDes Power and Signal Management
out connectivity to up to five PCI Express devices. The figure
The PEX 8606 provides low power capability that is fully
also shows how some of the ports can be bridged to provide
compliant with the PCI Express power management
PCI slots or Generic devices through the use of the PEX
specification. In addition, the SerDes physical links can be
8311 and PEX 8112 PCIe bridging devices.
turned off when unused for even lower power. The PEX 8606
supports software control of the SerDes outputs to allow