This document contains data proprietary to PUI Audio Inc. Any use or reproduction, in any form, without prior written permission of PUI Audio Inc. is prohibited. 2020, PUI Audio Inc. Data Sheet DMM-4026-B-EB-R PUI Audio is proud to release a line of high-fidelity MEMS wide-band microphones that cover 20 Hz up to 18 kHzand up to 20 kHz on some modelsand consistency of 1 dB across the entire frequency response. Quickly test and prototype the bottom-firing DMM-4026-B-EB-R with this evaluation board. Specifications Parameters Condition Values Units Directivity Omnidirectional 1 kHz 50cm with 94 dB source Sensitivity 0 dB=1V/Pa -261 dB Data Format 1/2 Cycle PDM Rated Voltage - 1.8 VDC Operating Voltage Range - 1.5 to 3.6 VDC Full Power Mode 820 ~ 1000 A Current Draw Low Power Mode 400 ~ 450 A Signal-to-Noise Ratio Full Power Mode 63 dB (1kHz, 94 dB input, A-weighted) Low Power Mode 61 dB Frequency Range 20~18,000 Hz Total Harmonic Distortion (typical) 94 dB 50cm, 1 kHz acoustic source 0.5% - Full Power Mode 123 dB Acoustic Overload Point SPL 50cm with 10% THD 1 kHz (AOP) Low Power Mode 120 dB SPL 50cm with 10% THD 1 kHz Environmental Compliances RoHS/Halogen Free 100 mVpp Square Wave Power Supply Rejection 217 Hz, A-weighted -86 dBFS Load Capacitance 140 pF Max Voltage on any Pin 4 VDC Maximum SPL Before Damage (Source 50cm from microphone) 160 dB Max Mechanical Shock 10,000 Gs Max Vibration Pre-MIL-STD-883 Method 2007, Test Condition B Operating Temp (VDD <3.0V) -40 ~ +100 C Operating Temp (VDD >3.0V) -40 ~ +70 C Storage Temperature -40 ~ +125 C PUI Audio, Inc., 3541 Stop Eight Road, Dayton, OH 45414 Tel: (937) 415-5901 Fax: (937) 415-5925 This document contains data proprietary to PUI Audio Inc. Any use or reproduction, in any form, without prior written permission of PUI Audio Inc. is prohibited. 2020, PUI Audio Inc. Operational Settings Parameters Condition Values Units Sleep Mode 0 ~ 250 kHz Clock Frequency Low Power Mode 500 ~ 800 kHz Full Power Mode 1.03 ~ 4.80 MHz For fCLK 2.4 MHz the duty cycle must be Duty Cycle in the range of 40 ~ 60% and for fCLK > 2.4 MHz the duty cycle must be 50% 40 ~ 60 % Logic Input High - 0.75*VDD ~ VDD + 0.3V Logic Input Low - -0.3 ~ 0.25*VDD Logic Output High - 0.75*VDD ~ VDD + 0.3V Logic Output Low - -0.3 ~ 0.25*VDD Timing Characteristics PUI Audio, Inc., 3541 Stop Eight Road, Dayton, OH 45414 Tel: (937) 415-5901 Fax: (937) 415-5925