5 4 3 2 1 CONTENTS: BLOCK DIAGRAM: D D PAGE1 - BLOCK DIAGRAM, CONTENTS PAGE2 - POWER, OSC 1V8 3V3 1V8 3V3 VBAT PAGE3 - I/O, eMMC CORE SMPS PAGE4 - SODIMM CONNECTOR 4Gbyte eMMC BCM2835 + 4Gb PoP LPDDR2 VDAC TV DAC REVISION HISTORY: GPIO 47:0 C C CSIx2, DSIx2 23/01/2014 - V1.0 TV, USB, HDMI 1V8 VDAC 3V3 VBAT JTAG 03/04/2014 - V1.1 - Production Version 200 pin DDR2 SODIMM edge connector B B A A RRRaaassspppbbbeeerrrrrryyy PPPiii 222000111444 wwwwwwwww...rrraaassspppbbbeeerrrrrryyypppiii...ooorrrggg TTTiiitttllleee DDDrrraaawwwnnn BBByyy RRRaaassspppbbbeeerrrrrryyy PPPiii CCCooommmpppuuuttteee MMMoooddduuullleee JJJaaammmeeesss AAAdddaaammmsss SSSiiizzzeee RRReeefff RRReeevvv AAA333 RRRPPPIII---CCCMMM 111...111 DDDaaattteee::: TTThhhuuurrrsssdddaaayyy,,, AAAppprrriiilll 000333,,, 222000111444 SSShhheeeeeettt 111 ooofff 444 5 4 3 2 1 EMMC DISABLE N GPIO0-27 VREF GPIO28-45 VREFVDD CORE 5 4 3 2 1 1V8 D D C5 U1D 220n P9 R8 XTAL N 1005 PLL 1V8 XTALN VBAT 3V3 1V8 VDAC OSC X1 PLL VDD XTAL P VBAT 3V3 1V8 VDAC N7 R9 1 3 PLL VDD OUT XTALP C1 C2 C3 C4 P7 PLL VDD 10u 10u 10u 10u TP1 TP2 TP3 TP4 TP5 C6 C7 2012 2012 2012 2012 1u 220n C8 19.2MHz C9 1005 1005 N8 18p 18p XOSC VDD 1005 1005 U18 AGND1 V1 AGND2 BCM2835 C C 1V8 3V3 U1A U1B VBAT SDC VDD B15 D18 H11 L5 SDRAM 1V8 1 SDC VDD OUT U1C GND1 VPP PWR1 C10 C14 K1 L1 1.0u H17 SDRAM 1V8 2 GND2 PWR2 220n 220n K17 C11 C15 C16 A13 C12 J2 C17 VDD CORE SDRAM 1V8 3 VDD BAT1 VDD OUT1 GND3 SMPS 1005 1005 T3 G13 220n 220n 1u A14 C13 J7 220n SDRAM 1V8 4 SDC VDD1 VDD BAT2 VDD OUT2 GND4 U17 H13 B13 D12 J8 1005 1005 1005 C18 C19 1005 SDRAM 1V8 5 SDC VDD2 VDD BAT3 VDD OUT3 GND5 V18 J5 10u B14 D13 10u J9 SDRAM 1V8 6 SDC VDD3 VDD BAT4 VDD OUT4 GND6 L12 2012 2012 J10 SDC VDD4 GND7 VDD OUT J11 GND8 A16 SDRAM VDD SLDO 1V8 1 C13 C20 C12 B16 C18 A15 J12 SLDO 1V8 2 SDRAM VDD OUT VDDBAT2 GND9 4.7u 220n 220n C21 C22 C24 C15 J13 VDD FB GND10 1608 1005 1005 C8 220n 1u 1u 3V3 C23 K7 T15 SDRAM VDD1 GND11 NVM VACC C16 1005 1005 1005 220n K8 SDRAM VDD2 GND12 C17 1005 A7 K9 D1 SDRAM VDD3 VDD CORE1 GND13 NVM VCC H12 G15 R1 A9 K10 ZQ0 SDRAM VDD4 VDD CORE2 GND14 T7 H18 10K D3 C27 C28 C29 K11 D2 ZQ1 SDRAM VDD5 VDD CORE3 GND15 NVM VCCQ J1 C25 C26 C30 1% E15 220n 220n 220n K12 SDRAM VDD6 VDD CORE4 GND16 R3 G12 R2 R3 220n 220n 1u 1005 1005 1005 1005 SDRAM VDD7 VDD CORE5 240R 240R T9 1005 1005 1005 H5 K13 SDRAM VDD8 VDD CORE6 GND17 B 1% 1% T17 RUN D15 H15 K14 B SDRAM VDD9 RUN VDD CORE7 GND18 1005 1005 H16 L2 RUN VDD CORE8 GND19 A1 K4 L7 GND1 VDD CORE9 GND20 A2 E18 VDDIO1 C31 L13 C32 C33 C34 L8 GND2 VDDIO1 OUT VDD CORE10 GND21 A3 100n L15 220n 220n 220n L9 GND3 VDD CORE11 GND22 A17 A10 N4 L10 C35 C36 C37 1005 1005 1005 1005 GND4 VDDIO1 1 VDD CORE12 GND23 A18 F15 220n 220n 1u N10 L11 GND5 VDDIO1 2 VDD CORE13 GND24 B1 G14 1005 1005 1005 D16 P15 GND6 VDDIO1 3 SR TEST VDD CORE14 B2 G17 L14 GND7 VDDIO1 4 GND25 B17 G18 M8 GND8 VDDIO1 5 GND26 B18 J14 C38 C39 M9 GND9 VDDIO1 6 GND27 C2 J16 A11 220n 220n M15 GND10 VDDIO1 7 SMPS PGND1 GND28 E3 K3 A12 1005 1005 N1 GND11 VDDIO1 8 SMPS PGND2 GND29 E14 M16 C40 C41 C42 U6 B11 N18 GND12 VDDIO1 9 AGND1 SMPS PGND3 GND30 F13 P18 220n 220n 220n V17 B12 P16 GND13 VDDIO1 10 AGND2 SMPS PGND4 GND31 F18 T4 1005 1005 1005 T18 GND14 VDDIO1 11 GND32 H9 T12 BCM2835 GND15 VDDIO1 12 H10 T16 BCM2835 GND16 VDDIO1 13 BCM2835 A A RRRaaassspppbbbeeerrrrrryyy PPPiii 222000111444 wwwwwwwww...rrraaassspppbbbeeerrrrrryyypppiii...ooorrrggg TTTiiitttllleee DDDrrraaawwwnnn BBByyy RRRaaassspppbbbeeerrrrrryyy PPPiii CCCooommmpppuuuttteee MMMoooddduuullleee JJJaaammmeeesss AAAdddaaammmsss SSSiiizzzeee RRReeefff RRReeevvv AAA333 RRRPPPIII---CCCMMM 111...111 DDDaaattteee::: TTThhhuuurrrsssdddaaayyy,,, AAAppprrriiilll 000333,,, 222000111444 SSShhheeeeeettt 222 ooofff 444 5 4 3 2 1 2 4