DATASHEET 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE ICS1894-33 Description Features The ICS1894-33 is a low-power, physical-layer device Supports category 5 cables and above with attenuation in (PHY) that supports the ISO/IEC 10Base-T and excess of 24dB at 100 MHz. 100Base-TX Carrier-Sense Multiple Access/Collision Single-chip, fully integrated PHY provides PCS, PMA, Detection (CSMA/CD) Ethernet standards, ISO/IEC PMD, and AUTONEG sub layers functions of IEEE 8802.3. It is intended for RMII Node applications and standard. includes the Auto-MDIX feature that automatically corrects 10Base-T and 100Base-TX ISO/IEC 8802.3 compliant crossover errors in plant wiring. MIIM (MDC/MDIO) management bus for PHY register The ICS1894-33 incorporates Digital-Signal Processing configuration (DSP) control in its Physical-Medium Dependent (PMD) RMII interface support with external 50 MHz system clock sub-layer. As a result, it can transmit and receive data on unshielded twisted-pair (UTP) category 5 cables with Single 3.3V power supply attenuation in excess of 24 dB at 100MHz. Highly configurable, supports: The ICS1894-33 provides a Serial-Management Interface Auto-Negotiation with Parallel detection for exchanging command and status information with a Node applications, managed or unmanaged Station-Management (STA) entity. The ICS1894-33 Media-Dependent Interface (MDI) can be configured to 10M or 100M half/full duplex modes provide half/full-duplex operation at data rates of 10 Mb/s or Auto-MDI/MDIX crossover correction 100Mb/s. Low-power CMOS (typically 300 mW) In addition, the ICS1894-33 includes a programmable LED Power-Down mode (typically 21mW) and interrupt output function. The LED outputs can be configured through registers to indicate the occurance of Programmable LEDs certain events such as LINK, ACTIVITY, etc. The purpose Interrupt output pin of the programmable interrupt output is to notify the PHY Fully integrated, DSP-based PMD includes: controller device immediately when a certain event happens instead of having the PHY controller continuously Adaptive equalization and baseline-wander poll the PHY. The events that could be used to generate correction interrupts are: receiver error, Jabber, page received, Transmit wave shaping and stream cipher parallel detect fault, link partner acknowledge, link status scrambler change, auto-negotiation complete, remote fault, etc. MLT-3 encoder and NRZ/NRZI encoder The ICS1894-33 has deep power modes that can result in Core power supply (3.3 V) significant power savings when the link is broken. 3.3 V/1.8 V VDDIO operation supported Applications: NIC cards, PC motherboards, switches, Smart power control with deep power down feature routers, DSL and cable modems, game machines, printers, network connected appliances, and industrial equipment. Available in 32-pin (5mm x 5mm) QFN package, Pb-free Available in Industrial Temp and Lead Free IDT 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 1 ICS1894-33 REV A 021612ICS1894-33 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Block Diagram 100Base-T PCS PMA TP PMD Framer Clock Recovery MLT-3 10/100 RMII Twisted- Interface Integrated Parallel to Serial Link Monitor Stream Cipher MAC 4B/5B Signal Detection Adaptive Equalizer Pair MUX Switch Interface Error Detection Baseline Wander Interface to Correction Magnetics Modules and 10Base-T RJ45 Connector MII Low-Jitter Smart Power Auto- Configuration Extended MII Clock Control Negotiation and Status Register Management Synthesizer Block Set Interface Clock Power LEDs and PHY Address Pin Assignment 25 1 TXD0 TP AP TXEN TP AN SPEED VSS NLG32 With Ground NOD/RXER VDD Connecting to Thermal Pad ANSEL TP BN VDDIO TP BP RMII/RXDV VDD FDPX/RXD0 17 TCSR 9 32-pin 5mm x 5mm QFN IDT 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 2 ICS1894-33 REV A 021612 P1/ISO/LED1 VSS RESET N P0/LED0 P2/INT REFIN MDIO NC MDC VSS AMDIX VSS TXD1 P3 VDDD RXTR1RXD1