7005S35J Renesas

HIGH-SPEED 7005S/L 8K x 8 DUAL-PORT STATIC RAM Features True Dual-Ported memory cells which allow simultaneous M/S = H for BUSY output flag on Master, reads of the same memory location M/S = L for BUSY input on Slave High-speed access Interrupt Flag Commercial:15/17/20/25/35ns (max.) On-chip port arbitration logic Industrial: 20ns (max.) Full on-chip hardware support of semaphore signaling Military: 20/25/35/55/70ns (max.) between ports Low-power operation Fully asynchronous operation from either port IDT7005S Devices are capable of withstanding greater than 2001V Active: 750mW (typ.) electrostatic discharge Standby: 5mW (typ.) Battery backup operation2V data retention IDT7005L TTL-compatible, single 5V (10%) power supply Active: 700mW (typ.) Available in 68-pin PGA, PLCC and a 64-pin thin quad Standby: 1mW (typ.) flatpack IDT7005 easily expands data bus width to 16 bits or more Industrial temperature range (-40C to +85C) is available for using the Master/Slave select when cascading more than selected speeds one device Green parts available, see ordering information Functional Block Diagram OER OEL CEL CER R/WL R/WR I/O0L-I/O7L I/O0R-I/O7R I/O I/O Control Control (1,2) (1,2) BUSYL BUSYR A12L A12R Address MEMORY Address Decoder ARRAY Decoder A0L A0R 13 13 ARBITRATION CEL INTERRUPT CER OEL SEMAPHORE OER LOGIC R/WR R/WL SEMR SEML M/S (2) (2) INTR INTL 2738 drw 01 NOTES: 1. (MASTER): BUSY is output (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull. 1 Feb.14.207005S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Description The IDT7005 is a high-speed 8K x 8 Dual-Port Static RAM. The Fabricated using CMOS high-performance technology, these de- IDT7005 is designed to be used as a stand-alone 64K-bit Dual-Port RAM vices typically operate on only 750mW of power. Low-power (L) versions or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or- offer battery backup data retention capability with typical power consump- more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM tion of 500W from a 2V battery. approach in 16-bit or wider memory system applications results in full- The IDT7005 is packaged in a ceramic 68-pin PGA, 68-pin PLCC speed, error-free operation without the need for additional discrete logic. and a 64-pin thin quad flatpack, (TQFP). Military grade product is This device provides two independent ports with separate control, manufactured in compliance with MIL-PRF-38535 QML making it ideally address, and I/O pins that permit independent, asynchronous access for suited to military temperature applications demanding the highest level of reads or writes to any location in memory. An automatic power down performance and reliability. feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. (1,2,3) Pin Configurations 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 I/O7R 27 9 I/O1L N/C 28 8 I/O0L OER 29 7 N/C R/WR 30 6 OEL SEMR 31 5 R/WL CER 32 4 SEML N/C 33 3 CEL N/C 34 7005 2 N/C GND 35 (4) 1 PLG68 N/C A12R 36 68 VCC 68-Pin PLCC A11R 37 67 A12L Top View A10R 38 66 A11L A9R 39 65 A10L A8R 40 64 A9L A7R 41 63 A8L A6R 42 62 A7L A5R 43 61 A6L 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 2738 drw 02 46 45 44 43 42 41 40 39 38 37 36 35 34 33 48 47 A5L A5R 49 32 A6L 50 31 A6R A7L 51 30 A7R A8L 52 29 A8R A9L 53 28 A9R A10L 54 27 A10R A11L 55 26 A11R A12L 7005 56 25 A12R (4) VCC PNG64 57 24 GND N/C N/C 58 23 64-Pin TQFP CEL 59 CER 22 Top View SEML 60 21 SEMR R/WL 61 R/WR 20 OEL OER 62 19 NOTES: I/O0L 63 18 I/O7R 1. All VCC pins must be connected to power supply. I/O1L I/O6R 64 17 2. All GND pins must be connected to ground supply. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 3. PLG68 package body is approximately .95 in x .95 in x .12 in. PNG64 package body is approximately 14mm x 14mm x 1.4mm. 2738 drw 03 4. This package code is used to reference the package diagram. 6.422 Feb.14.20 A4R 26 I/O6R A3R I/O5R A2R I/O4R A1R I/O3R A0R VCC INTR I/O2R BUSYR I/O1R M/S I/O0R GND GND BUSYL VCC INTL I/O7L A0L I/O6L A1L GND A2L I/O5L A3L I/O4L A4L I/O3L A5L I/O2L I/O2L A4L I/O3L A3L I/O4L A2L I/O5L A1L GND A0L I/O6L INTL I/O7L BUSYL VCC GND M/S GND BUSYR I/O0R INTR I/O1R I/O2R A0R VCC A1R I/O3R A2R I/O4R A3R I/O5R A4R