70V06L15PFG Renesas

HIGH-SPEED 3.3V 70V06L 16K x 8 DUAL-PORT STATIC RAM Features True Dual-Ported memory cells which allow simultaneous M/S = VIH for BUSY output flag on Master reads of the same memory location M/S = VIL for BUSY input on Slave High-speed access Interrupt Flag Commercial: 15ns (max.) On-chip port arbitration logic Industrial: 20ns (max.) Full on-chip hardware support of semaphore signaling Low-power operation between ports IDT70V06L Fully asynchronous operation from either port Active: 380mW (typ.) Battery backup operation2V data retention Standby: 660W (typ.) TTL-compatible, single 3.3V (0.3V) power supply IDT70V06 easily expands data bus width to 16 bits or more Available in a 68-pin PLCC and a 64-pin TQFP using the Master/Slave select when cascading more than Industrial temperature range (-40C to +85C) is available one device for selected speeds Green parts available, see ordering information Functional Block Diagram OEL OER CEL CER R/WL R/WR , I/O0L- I/O7L I/O0R-I/O7R I/O I/O Control Control (1,2) (1,2) BUSYL BUSYR A13L A13R Address MEMORY Address Decoder ARRAY Decoder A0L A0R 14 14 ARBITRATION INTERRUPT CEL CER SEMAPHORE OEL OER LOGIC R/WR R/WL SEML SEMR M/S (2) (2) INTL INTR 2942 drw 01 NOTES: 1. (MASTER): BUSY is output (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull. 1 Feb.07.20 6.0761 70V06L High-Speed 3.3V 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges This device provides two independent ports with separate control, Description address, and I/O pins that permit independent, asynchronous access for The IDT70V06 is a high-speed 16K x 8 Dual-Port Static RAM. The reads or writes to any location in memory. An automatic power down IDT70V06 is designed to be used as a stand-alone 128K-bit Dual-Port feature controlled by CE permits the on-chip circuitry of each port to enter Static RAM or as a combination MASTER/SLAVE Dual-Port Static RAM a very low standby power mode. for 16-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual- Fabricated using CMOS high-performance technology, these de- Port Static RAM approach in 16-bit or wider memory system applications vices typically operate on only 400mW of power. results in full-speed, error-free operation without the need for additional The IDT70V06 is packaged in a 68-pin PLCC and a 64-pin thin quad discrete logic. flatpack (TQFP). (1,2,3) Pin Configurations 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 I/O7R 9 I/O1L 27 N/C 28 8 I/O0L 29 OER 7 N/C R/WR 30 6 OEL 31 5 R/WL SEMR 32 CER 4 SEML 33 3 N/C CEL 34 2 A13R N/C 70V06 35 (4) Vss 1 A13L PLG68 A12R 36 68 VDD 68-Pin PLCC 37 67 A11R A12L Top View A10R 38 66 A11L 39 A9R 65 A10L A8R 40 64 A9L 41 A7R 63 A8L 42 A6R 62 A7L 43 A5R A6L 56 44 45 46 47 48 49 50 51 52 53 54 55 57 58 59 60 2942 drw 02 46 45 44 43 42 41 40 39 38 37 36 35 34 33 48 47 49 32 A5L A5R A6L 50 31 A6R A7L 51 30 A7R A8L 52 29 A8R A9L 53 28 A9R A10L 54 27 A10R A11L 55 26 A11R A12L 56 70V06 25 A12R (4) PNG64 VDD 57 24 VSS A13L 58 A13R 23 64-Pin TQFP 59 CEL CER Top View 22 SEML 60 21 SEMR R/WL 61 20 R/WR OEL 62 OER 19 NOTES: I/O0L 63 18 I/O7R 1. All VDD pins must be connected to power supply. I/O1L 64 17 I/O6R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2. All VSS pins must be connected to ground supply. 3. PLG68 package body is approximately .95 in x .95 in x .17 in 2942 drw 03 PNG64 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 2 Feb.07.20 A4R I/O6R A3R I/O5R A2R I/O4R A1R I/O3R A0R VDD INTR I/O2R BUSYR I/O1R M/S I/O0R VSS VSS BUSYL VDD INTL I/O7L A0L I/O6L A1L VSS A2L I/O5L A3L I/O4L A4L I/O3L A5L I/O2L I/O2L A4L I/O3L A3L I/O4L A2L I/O5L A1L VSS A0L I/O6L INTL BUSYL I/O7L VDD VSS VSS M/S BUSYR I/O0R I/O1R INTR I/O2R A0R VDD A1R I/O3R A2R I/O4R A3R I/O5R A4R