HIGH-SPEED 3.3V 32K x 36 IDT70V3579S SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE address inputs 133MHz True Dual-Port memory cells which allow simultaneous Data input, address, byte enable and control registers access of the same memory location Self-timed write allows fast cycle time High-speed clock to data access Separate byte controls for multiplexed bus and bus Commercial: 4.2/5/6ns (max.) matching compatibility Industrial: 5/6ns (max) LVTTL- compatible, single 3.3V (150mV) power supply for Pipelined output mode core Counter enable and reset features LVTTL compatible, selectable 3.3V (150mV)/2.5V (125mV) Dual chip enables allow for depth expansion without power supply for I/Os and control signals on each port additional logic Industrial temperature range (-40C to +85C) is Full synchronous operation on both ports available for selected speeds 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth) Available in a 208-pin Plastic Quad Flatpack (PQFP) and Fast 4.2ns clock to data out 208-pin fine pitch Ball Grid Array, and 256-pin Ball Grid 1.8ns setup to clock and 0.7ns hold on all control, data, and Array BE3L BE3R BE2R BE2L BE1L BE1R BE0L BE0R L R/W WR R/ B B B B B B B B W W W W W WW W 0 1 2 3 3 2 1 0 CE0L L L L L R R R R CE0R 1L CE CE1R OEL OER Dout0-8 L Dout0-8 R Dout9-17 L Dout9-17 R Dout18-26 L Dout18-26 R Dout27-35 L Dout27-35 R 32K x 36 MEMORY ARRAY 0L 35L I/O -I/O Din L 0R 35R Din R I/O -I/O , CLKL CLKR 14L A A14R Counter/ Counter/ A0L A0R Address ADDR L ADDR R Address CNTRSTL CNTRSTR Reg. Reg. ADSR ADSL CNTENL CNTENR 4830 tbl 01 1 DSC 4830/13 2001 Integrated Device Technology, Inc.IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges The IDT70V3579 is a high-speed 32K x 36 bit synchronous Dual- bidirectional data flow in bursts. An automatic power down feature, Port RAM. The memory array utilizes Dual-Port memory cells to allow controlled by CE0 and CE1, permits the on-chip circuitry of each port to simultaneous access of any address from both ports. Registers on enter a very low standby power mode. control, data, and address inputs provide minimal setup and hold The 70V3579 can support an operating voltage of either 3.3V or 2.5V times. The timing latitude provided by this approach allows systems on one or both ports, controllable by the OPT pins. The power supply for to be designed with very short cycle times. With an input data register, the the core of the device (VDD) remains at 3.3V. IDT70V3579 has been optimized for applications having unidirectional or A1 A2 A3 A6 A7 A8 A9 A11 A12 A13 A14 A17 A4 A5 A10 A15 A16 IO19L IO18L VSS NC NC NC A12L A8L BE1L VDD CLKL CNTENL A4L A0L OPTL I/O17L VSS B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 I/O20R VSS I/O18R VSS NC A13L A9L BE2L CE0L VSS ADSL A5L A1L VSS VDDQR I/O16L I/O15R C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C16 C14 C15 C17 VDDQL I/O19R VDDQR VDD NC A14L A10L BE3L CE1L VSS R/WL A6L A2L V I/O I/O15L V DD 16R SS D1 D2 D6 D9 D11 D3 D4 D5 D7 D8 D10 D12 D13 D14 D15 D16 D17 I/O22L VSS I/O NC A11L A BE VDD OE CNTRSTL A V I/O V I/O I/O 21L I/O20L 7L 0L L 3L DD 17R DDQL 14L 14R E1 E2 E3 E4 E14 E15 E16 E17 I/O23L I/O22R VDDQR I/O21R I/O12L I/O13R VSS I/O13L F1 F2 F3 F4 F14 F15 F16 F17 VDDQL I/O23R I/O24L VSS VSS I/O12R I/O11L VDDQR G1 G2 G3 G4 G14 G15 G16 G17 I/O26L VSS I/O25L I/O24R I/O9L VDDQL I/O10L I/O11R H3 H4 H1 H2 H14 H15 H16 H17 70V3579BF VDD I/O26R VDDQR I/O25R VSS I/O10R VDD IO9R (5) BF-208 J1 J2 J3 J4 J14 J15 J16 J17 VDDQL VDD VSS VSS VSS VDD VSS VDDQR 208-Pin fpBGA K1 K2 K3 K4 K14 K15 K16 K17 (6) I/O28R VSS I/O27R VSS Top View I/O7R VDDQL I/O8R VSS L3 L4 L15 L16 L17 L1 L2 L14 VDDQR I/O27L I/O7L VSS I/O8L I/O29R I/O28L I/O6R M1 M2 M3 M4 M14 M15 M16 M17 VDDQL I/O29L I/O30R VSS VSS I/O6L I/O5R VDDQR N1 N2 N3 N4 N14 N15 N16 N17 I/O4R I/O5L I/O31L VSS I/O31R I/O30L I/O3R VDDQL P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 I/O32R I/O32L VDDQR I/O35R NC NC A12R A8R BE1R VDD CLKR CNTENR A4R I/O2L I/O3L VSS I/O4L R5 R6 R7 R8 R9 R10 R11 R16 R1 R2 R3 R4 R12 R13 R14 R15 R17 NC A13R A9R BE2R CE0R VSS ADSR I/O1R VSS I/O33L I/O34R NC A5R A1R VSS VDDQL VDDQR T1 T2 T3 T4 T5 T8 T9 T15 T16 T17 T6 T7 T10 T11 T12 T13 T14 I/O33R I/O34L VDDQL VSS NC A14R A10R BE3R CE1R VSS R/WR A6R A2R VSS I/O0R VSS I/O2R U1 U2 U3 U4 U5 U6 U7 U17 U8 U9 U10 U12 U13 U14 U16 U15 VSS I/O35L VDD NC NC A11R A7R I/O1L BE0R VDD OER A3R A0R VDD OPTR I/O0L , 4830 drw 02c NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V). SS pins must be connected to ground supply. 3. All V 4. Package body is approximately 15mm x 15mm x 1.4mm, with 0.8mm ball-pitch. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 6.42 2