70V657S10BFG Renesas

70V659/58/57S HIGH-SPEED 3.3V 128/64/32K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM Features True Dual-Port memory cells which allow simultaneous Full on-chip hardware support of semaphore signaling access of the same memory location between ports High-speed access Fully asynchronous operation from either port Commercial: 10/12/15ns (max.) Separate byte controls for multiplexed bus and bus Industrial: 12ns (max.) matching compatibility Dual chip enables allow for depth expansion without Supports JTAG features compliant to IEEE 1149.1 external logic LVTTL-compatible, single 3.3V (150mV) power supply for IDT70V659/58/57 easily expands data bus width to 72 bits core or more using the Master/Slave select when cascading LVTTL-compatible, selectable 3.3V (150mV)/2.5V (100mV) more than one device power supply for I/Os and control signals on each port M/S = VIH for BUSY output flag on Master, Available in a 208-pin Plastic Quad Flatpack, 208-ball fine M/S = VIL for BUSY input on Slave pitch Ball Grid Array, and 256-ball Ball Grid Array Busy and Interrupt Flags Industrial temperature range (40C to +85C) is available On-chip port arbitration logic for selected speeds Green parts available, see ordering information Functional Block Diagram BE3L BE3R BE2L BE2R BE1L BE1R BE0L BE0R R/WL R/WR B B B B B B B B E E E E E E E E 0 1 2 3 3 2 1 0 CE0L CE0R L L L L R R R R CE1L CE1R OEL OER Dout0-8 L Dout0-8 R Dout9-17 L Dout9-17 R Dout18-26 L Dout18-26 R Dout27-35 L Dout27-35 R 128/64/32K x 36 MEMORY ARRAY I/O0L- I/O35L Di n L Di n R I/O0R -I/O35R (1) A16R (1) A16 L Address Address ADDR L ADDR R Decoder Decoder A0R A0L CE0L ARBITRATION CE0R CE1L CE1R INTERRUPT OEL OER SEMAPHORE LOGIC R/WL R/WR (2,3) (2,3) BUSYL BUSYR SEML M/S SEMR (3) (3) INTL INTR TMS TDI TCK JTAG TDO TRST NOTES: 4869 drw 01 1. A16 is a NC for IDT70V658. Also, Addresses A16 and A15 are NC s for IDT70V657. IL) and an output when it is a Master (M/S=VIH). 2. BUSY is an input as a Slave (M/S=V 3. BUSY and INT are non-tri-state totem-pole outputs (push-pull). 1 Aug.23.2170V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description The IDT70V659/58/57 is a high-speed 128/64/32K x 36 Asynchro- This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for nous Dual-Port Static RAM. The IDT70V659/58/57 is designed to be used reads or writes to any location in memory. An automatic power down as a stand-alone 4/2/1Mbit Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the feature controlled by the chip enables (either CE0 or CE1) permit the MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider memory on-chip circuitry of each port to enter a very low standby power mode. The 70V659/58/57 can support an operating voltage of either 3.3V system applications results in full-speed, error-free operation without the or 2.5V on one or both ports, controlled by the OPT pins. The power supply need for additional discrete logic. for the core of the device (VDD) remains at 3.3V. (3,4,5,6) Pin Configuration VSS 157 VSS 104 VDDQR 158 VDDQL 103 I/O17R 159 102 I/O0R I/O17L 160 101 I/O0L OPTL 161 100 OPTR VSS 162 99 VSS VDD 163 98 VSS VDD 164 97 VDD A0L 165 A0R A1L 166 95 A1R A2L 167 94 A2R A3L 168 93 A3R A4L 169 92 A4R A5L 170 91 A5R A6L 171 90 A6R NC 172 89 M/S 173 INTL 88 INTR BUSYL 174 87 BUSYR R/WL 175 86 R/WR OEL 70V659/58/57 176 85 OER SEML 84 177 SEMR (7) DR208 VSS 178 83 VSS VSS 179 82 VSS (7) DRG208 VDD 180 81 VDD VDD 181 80 VDD CE0L 182 79 CE0R CE1L 183 78 CE1R 208-Pin PQFP BE0L 184 77 BE0R BE1L 185 76 BE1R Top View BE2L 186 75 BE2R 187 BE3L 74 BE3R A7L 188 73 A7R A8L 189 A8R 72 A9L 190 71 A9R A10L 191 70 A10R A11L 192 A11R A12L 193 68 A12R A13L 194 A13R 67 A14L 195 A14R 66 (2) (2) A15L 196 65 A15R (1) A16L (1) 197 64 A16R NC 198 63 NC NC 199 62 NC NC 200 61 NC TDO 201 60 TRST 202 TDI 59 TCK VDD 203 58 TMS VSS 204 57 VDD I/O18L 205 56 I/O35L I/O18R 206 55 I/O35R VDDQR 207 54 VDDQL Vss 208 53 VSS 4869 drw 02 NOTES: 1. Pin is a NC for IDT70V658 and IDT70V657. 2. Pin is a NC for IDT70V657. DD pins must be connected to 3.3V power supply. 3. All V 4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (3.3V) and 2.5V if OPT pin for that port is set to VSS (0V). 5. All VSS pins must be connected to ground. 6. Package body is approximately 28mm x 28mm x 3.5mm. 7. This package code is used to reference the package diagram. 2 Aug.23. 21 1 I/O16L I/O19L 156 2 I/O16R I/O19R 155 I/O15L I/O20L 3 154 4 I/O15R I/O20R 153 5 VSS VDDQL 152 VDDQL VSS 6 151 I/O21L 7 I/O14L 150 8 I/O14R I/O21R 149 I/O13L I/O22L 9 148 I/O13R I/O22R 10 147 VDDQR 11 VSS 146 VDDQR VSS 12 145 I/O12L I/O23L 13 144 I/O12R I/O23R 14 143 15 I/O11L I/O24L 142 I/O11R I/O24R 16 141 VSS VDDQL 17 140 VSS 18 VDDQL 139 I/O10L I/O25L 19 138 I/O10R I/O25R 20 137 I/O9L I/O26L 21 136 I/O9R I/O26R 22 135 VSS VDDQR 23 134 VDDQR VSS 24 133 VDD VDD 25 132 VDD VDD 26 131 VSS VSS 27 130 VSS VSS 28 129 VDDQL VSS 29 128 VDDQL VSS 30 127 I/O8R I/O27R 31 126 I/O8L I/O27L 32 125 I/O7R I/O28R 33 124 I/O7L I/O28L 34 123 VSS VDDQR 35 122 VDDQR VSS 36 121 I/O6R I/O29R 37 120 I/O6L I/O29L 38 119 I/O5R I/O30R 39 118 I/O5L I/O30L 40 117 VSS VDDQL 41 116 VDDQL VSS 42 115 I/O4R I/O31R 43 114 I/O4L I/O31L 44 113 I/O3R I/O32R 45 112 I/O3L I/O32L 46 111 VSS VDDQR 47 110 VDDQR VSS 48 109 I/O2R I/O33R 49 108 I/O2L I/O33L 50 107 51 I/O1R I/O34R 106 I/O1L I/O34L 52 105 69 96