HIGH SPEED IDT7133SA/LA 2K X 16 DUAL-PORT IDT7143SA/LA SRAM Features High-speed access BUSY output flag on IDT7133 BUSY input on IDT7143 Fully asynchronous operation from either port Military: 25/35/45/55/70/90ns (max.) Industrial: 25/35/55ns (max.) Battery backup operation2V data retention Commercial: 20/25/35/45/55/70/90ns (max.) TTL-compatible single 5V (10%) power supply Low-power operation Available in 68-pin ceramic PGA, Flatpack, PLCC and 100- IDT7133/43SA pin TQFP Active: 1150mW (typ.) Military product compliant to MIL-PRF-38535 QML Industrial temperature range (40C to +85C) is available Standby: 5mW (typ.) IDT7133/43LA for selected speeds Active: 1050mW (typ.) Green parts available, see ordering information Standby: 1mW (typ.) Description Versatile control for write: separate write control for lower and upper byte of each port The IDT7133/7143 are high-speed 2K x 16 Dual-Port Static RAMs. MASTER IDT7133 easily expands data bus width to 32 bits The IDT7133 is designed to be used as a stand-alone 16-bit Dual-Port or more using SLAVE IDT7143 On-chip port arbitration logic (IDT7133 only) Functional Block Diagram R/WRUB R/WLUB CER CEL R/WLLB R/WRLB OER OEL I/O8L-I/O15L I/O8R-I/O15R I/O I/O CONTROL CONTROL I/O0L - I/O7L I/O0R-I/O7R (1) (1) BUSYR BUSYL A10R A10L MEMORY ADDRESS ADDRESS ARRAY DECODER DECODER A0L A0R 11 11 ARBITRATION CEL CER LOGIC (IDT7133 ONLY) 2746 drw 01 NOTE: 1. IDT7133 (MASTER): BUSY is open drain output and requires pull-up resistor. IDT7143 (SLAVE): BUSY is input. OCTOBER 2008 1 DSC 2746/13 2008 Integrated Device Technology, Inc.IDT7133SA/LA, IDT7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges RAM or as a MASTER Dual-Port RAM together with the IDT7143 port to enter a very low standby power mode. SLAVE Dual-Port in 32-bit-or-more word width systems. Using the IDT Fabricated using IDTs CMOS high-performance technology, these MASTER/SLAVE Dual-Port RAM approach in 32-bit-or-wider memory devices typically operate on only 1,150mW of power. Low-power (LA) system applications results in full-speed, error-free operation without the versions offer battery backup data retention capability, with each port need for additional discrete logic. typically consuming 200W for a 2V battery. Both devices provide two independent ports with separate control, The IDT7133/7143 devices have identical pinouts. Each is packed address, and I/O pins that permit independent, asynchronous access in a 68-pin ceramic PGA, 68-pin flatpack, 68-pin PLCC and 100-pin for reads or writes to any location in memory. An automatic power TQFP. Military grade product is manufactured in compliance with the down feature, controlled by CE, permits the on-chip circuitry of each latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. (1,2,3) Pin Configurations INDEX 98 7 654 3 2 68 67 66 65 64 63 62 61 I/O9L 60 10 A6L 1 I/O10L 59 11 A5L I/O11L 12 58 A4L I/O12L 13 57 A3L 56 I/O13L 14 A2L I/O14L 55 15 A1L I/O15L 54 16 IDT7133/43 A0L (4) J68-1 / F68-1 (1) VCC 53 17 BUSYL (2) GND 18 52 CEL 68-Pin PLCC/Flatpack I/O0R (5) 51 CER 19 Top View I/O1R 50 20 BUSYR I/O2R 49 21 A0R I/O3R 48 22 A1R I/O4R 47 23 A2R I/O5R 24 46 A3R I/O6R 25 45 A4R I/O7R 44 26 A5R 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 , 2746 drw 02 Index 1009998979695949392919089 88 87 8685 848382 8180 79787776 N/C 1 N/C 75 N/C N/C 2 74 N/C 3 N/C 73 N/C 4 N/C 72 A5L I/O10L 5 71 I/O11L 6 A4L 70 A3L I/O12L 7 69 I/O13L 8 A2L 68 A1L GND 9 67 10 IDT7133/43PF A0L I/O14L 66 (4) PN100-1 N/C I/O15L 11 65 VCC 12 64 BUSYL 100-Pin TQFP 13 GND GND 63 (5) Top View I/O0R 14 62 N/C BUSYR I/O1R 15 61 I/O2R 16 60 N/C VCC A0R 17 59 A1R I/O3R 18 58 NOTES: I/O4R A2R 19 57 1. Both VCC pins must be connected to the power supply to ensure reliable A3R I/O5R 20 56 operation. I/O6R 21 55 A4R 2. Both GND pins must be connected to the ground supply to ensure reliable N/C N/C 22 54 N/C 23 53 N/C operation. N/C N/C 24 52 3. J68-Package body is approximately 0.95 in x 0.95 in x 0.17 in. N/C N/C 25 51 , 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 F68-Package body is approximately 1.18 in x 1.18 in x 0.16 in. 2746 drw 03 PN100-Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. 6.42 2 I/O8R I/O8L I/O9R I/O7L I/O10R I/O6L I/O5L I/O11R I/O12R I/O4L I/O3L I/O13R I/O2L I/O14R I/O15R I/O1L (2) GND I/O0L (1) R/WRUB VCC R/WLUB R/WRLB R/WLLB OER OEL A10R A9R A10L A9L A8R A8L A7R A7L A6R I/O7R I/O9L I/O8L I/O8R I/O9R I/O7L I/O6L I/O10R I/O11R I/O5L 12R I/O4L I/O I/O13R I/O3L I/O14R I/O2L GND GND 15R I/O1L I/O OER I/O0L R/WRLB OEL VCC GND N/C R/WLLB CER N/C R/WRUB CEL R/WLUB N/C N/C N/C N/C N/C N/C A10R A10L A9R A9L A8R A7R A8L A7L A6R A6L A5R