71V416L10PHG Renesas

71V416S 3.3V CMOS Static RAM 71V416L 4 Meg (256K x 16-Bit) Features Description 256K x 16 advanced high-speed CMOS Static RAM The IDT71V416 is a 4,194,304-bit high-speed Static RAM organized JEDEC Center Power / GND pinout for reduced noise. as 256K x 16. It is fabricated using high-performance, high-reliability Equal access and cycle times CMOS technology. This state-of-the-art technology, combined with inno- Commercial and Industrial: 10/12/15ns vative circuit design techniques, provides a cost-effective solution for high- One Chip Select plus one Output Enable pin speed memory needs. Bidirectional data inputs and outputs directly The IDT71V416 has an output enable pin which operates as fast as LVTTL-compatible 5ns, with address access times as fast as 10ns. All bidirectional inputs and Low power consumption via chip deselect outputs of the IDT71V416 are LVTTL-compatible and operation is from a Upper and Lower Byte Enable Pins single 3.3V supply. Fully static asynchronous circuitry is used, requiring Single 3.3V power supply no clocks or refresh for operation. Available in 44-pin, 400 mil plastic SOJ package and a 44- The IDT71V416 is packaged in a 44-pin, 400 mil Plastic SOJ and a pin, 400 mil TSOP Type II package and a 48 ball grid array, 44-pin, 400 mil TSOP Type II package and a 48 ball grid array, 9mm x 9mm x 9mm package. 9mm package. Green parts available, see ordering information Functional Block Diagram Output OE Enable Buffer Address Row / Column A0 - A17 Buffers Decoders High 8 8 Byte I/O 15 Output Chip Buffer CS Select Buffer High 8 8 Byte I/O 8 Write Sense 4,194,304-bit Buffer 16 Amps Memory and Array Write Drivers Write Low 8 8 WE Byte Enable I/O 7 Output Buffer Buffer Low 8 8 Byte I/O 0 Write Buffer BHE Byte Enable Buffers BLE 3624 drw 01 1 May.26.2171V416S, 71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges (2) (1) Pin Configurations - SOJ/TSOP Pin Configurations - BGA A0 1 A17 44 BE48, BEG48 A1 2 43 A16 A2 3 A15 42 1 2 3 456 A3 41 4 OE A4 40 BHE 5 A BLE OE A0 A1 A2 NC CS 6 39 BLE I/O0 38 I/O15 7 PHG44 BI/O0 BHE A3 A4 CS I/O8 or I/O1 8 37 I/O14 PBG44 I/O2 9 36 I/O13 CI/O1 I/O2 A5 A6 I/O10 I/O9 35 I/O3 10 I/O12 44-Pin 34 VDD 11 VSS DVSS I/O3 A17 A7 I/O11 VDD TSOP 33 VDD VSS 12 SOJ I/O11 I/O4 13 32 EVDD I/O4 NC A16 I/O12 VSS TopView 31 I/O5 14 I/O10 30 I/O6 I/O9 15 FI/O6 I/O5 A14 A15 I/O13 I/O14 I/O7 29 I/O8 16 (1) 28 NC 17 WE GI/O7 NC A12 A13 I/O15 WE A14 27 A5 18 A6 26 A13 19 HNC A8 A9 A10 A11 NC 25 A7 A12 20 24 A11 3624 tbl 11 A8 21 A9 23 A10 22 Top View NOTE: 3624 drw 02 1. This text does not indicate orientation of actual part-marking. NOTES: 1. Pin 28 can either be a NC or connected to Vss. 2. This text does not indicate orientation of actual part-marking. SOJ Capacitance (TA = +25C, f = 1.0MHz) (1) Symbol Parameter Conditions Max. Unit Pin Descriptions CIN Input Capacitance VIN = 3dV 7 pF A0 - A17 Address Inputs Input CI/O I/O Capacitance VOUT = 3dV 8 pF Chip Select Input CS 3624 tbl 02 WE Write Enable Input Output Enable Input OE BGA Capacitance BHE High Byte Enable Input (TA = +25C, f = 1.0MHz) (1) Low Byte Enable Input Symbol Parameter Conditions Max. Unit BLE I/O0 - I/O15 Data Input/Output I/O CIN Input Capacitance VIN = 3dV 6 pF VDD 3.3V Power Pwr CI/O I/O Capacitance VOUT = 3dV 7 pF 3624 tbl 02b VSS Ground Gnd NOTE: 1. This parameter is guaranteed by device characterization, but not production 3624 tbl 01 tested. 6.42 2 May.26.21