IDT72801 DUAL CMOS SyncFIFO IDT72811 DUAL 256 x 9, DUAL 512 x 9, IDT72821 DUAL 1,024 x 9, DUAL 2,048 x 9, IDT72831 DUAL 4,096 x 9, DUAL 8,192 x 9 IDT72841 IDT72851 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 Each of the two FIFOs (designated FIFO A and FIFO B) contained in the FEATURES: IDT72801/72811/72821/72831/72841/72851 has a 9-bit input data port (DA0 The IDT72801 is equivalent to two IDT72201 256 x 9 FIFOs - DA8, DB0 - DB8) and a 9-bit output data port (QA0 - QA8, QB0 - QB8). Each The IDT72811 is equivalent to two IDT72211 512 x 9 FIFOs input port is controlled by a free-running clock (WCLKA, WCLKB), and two Write The IDT72821 is equivalent to two IDT72221 1,024 x 9 FIFOs Enable pins (WENA1, WENA2, WENB1, WENB2). Data is written into each of The IDT72831 is equivalent to two IDT72231 2,048 x 9 FIFOs the two arrays on every rising clock edge of the Write Clock (WCLKA, WCLKB) The IDT72841 is equivalent to two IDT72241 4,096 x 9 FIFOs when the appropriate write enable pins are asserted. The IDT72851 is equivalent to two IDT72251 8,192 x 9 FIFOs The output port of each FIFO bank is controlled by its associated clock pin Offers optimal combination of large capacity, high speed, (RCLKA, RCLKB) and two Read Enable pins (RENA1, RENA2, RENB1, design flexibility and small footprint RENB2). The Read Clock can be tied to the Write Clock for single clock operation Ideal for prioritization, bidirectional, and width expansion or the two clocks can run asynchronous of one another for dual clock operation. applications An Output Enable pin (OEA, OEB) is provided on the read port of each FIFO 10 ns read/write cycle time for the IDT72801/72811/72821/72831/ for three-state output control. 72841/72851 Each of the two FIFOs has two fixed flags, Empty (EFA, EFB) and Full (FFA, Separate control lines and data lines for each FIFO FFB). Two programmable flags, Almost-Empty (PAEA, PAEB) and Almost-Full Separate Empty, Full, Programmable Almost-Empty and Almost- (PAFA, PAFB), are provided for each FIFO bank to improve memory utilization. Full flags for each FIFO If not programmed, the programmable flags default to empty+7 for PAEA and Enable puts output data lines in high-impedance state PAEB, and full-7 for PAFA and PAFB. Space-saving 64-pin Thin Quad Flat Pack (TQFP) and Slim Thin The IDT72801/72811/72821/72831/72841/72851 architecture lends itself Quad Flatpack (STQFP) to many flexible configurations such as: Industrial temperature range (40C to +85C) is available 2-level priority data buffering Green parts available, see ordering information Bidirectional operation Width expansion DESCRIPTION: Depth expansion The IDT72801/72811/72821/72831/72841/72851 are dual synchronous These FIFOs is fabricated using high-performance submicron CMOS (clocked) FIFOs. The device is functionally equivalent to two IDT72201/72211/ technology. 72221/72231/72241/72251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. FUNCTIONAL BLOCK DIAGRAM EFA WCLKB PAEA WCLKA WENB1 WENA1 DA0 - DA8 PAFA DB0 - DB8 LDA LDB FFA WENA2 WENB2 INPUT REGISTER OFFSET REGISTER INPUT REGISTER OFFSET REGISTER EFB FLAG WRITE CONTROL FLAG WRITE CONTROL PAEB LOGIC LOGIC LOGIC LOGIC PAFB FFB RAM ARRAY RAM ARRAY 256 x 9, 512 x 9, 256 x 9, 512 x 9, WRITE POINTER READ POINTER READ POINTER WRITE POINTER 1024 x 9, 2048 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9 4096 x 9, 8192 x 9 READ CONTROL READ CONTROL LOGIC LOGIC OUTPUT REGISTER OUTPUT REGISTER RESET LOGIC RESET LOGIC RCLKB RSA RSB OEA RCLKA OEB RENB1 QB0 - QB8 QA0 - QA8 RENA1 RENB2 RENA2 3034 drw 01 IDT, IDT logo and the SyncFIFO logo are registered trademarks of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE FEBRUARY 2018 1 DSC-3034/7TM IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO COMMERCIAL AND INDUSTRIAL DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9 TEMPERATURE RANGES PIN CONFIGURATION 48 QB0 QA1 1 47 FFB QA2 2 46 EFB QA3 3 OEB 45 QA4 4 RENB2 44 QA5 5 RCLKB 43 QA6 6 RENB1 42 QA7 7 GND 41 QA8 8 VCC 40 VCC 9 PAEB 39 WENA2/LDA 10 PAFB 38 WCLKA 11 DB0 37 WENA1 12 DB1 36 RSA 13 DB2 35 DA8 14 DB3 34 DA7 15 DB4 33 DA6 16 3034 drw 02 TQFP (PN64-1, order code: PF) STQFP (PP64-1, order code: TF) TOP VIEW 2 MARCH 2013 DA5 QA0 17 64 DA4 FFA 18 63 DA3 EFA 19 62 DA2 OEA 20 61 DA1 RENA2 21 60 DA0 RCLKA 22 59 PAFA RENA1 23 58 PAEA 24 GND 57 QB8 WENB2/LDB 25 56 WCLKB 26 QB7 55 WENB1 27 QB6 54 RSB 28 QB5 53 DB8 29 QB4 52 DB7 30 QB3 51 DB6 31 50 QB2 DB5 32 49 QB1