TM 3.3 VOLT CMOS SyncFIFO IDT72V205, IDT72V215, IDT72V225, IDT72V235, 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18 IDT72V245 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 Industrial temperature range (40C to +85C) is available FEATURES: Green parts available, see ordering information 256 x 18-bit organization array (IDT72V205) 512 x 18-bit organization array (IDT72V215) DESCRIPTION: 1,024 x 18-bit organization array (IDT72V225) 2,048 x 18-bit organization array (IDT72V235) The IDT72V205/72V215/72V225/72V235/72V245 are functionally com- 4,096 x 18-bit organization array (IDT72V245) patible versions of the IDT72205LB/72215LB/72225LB/72235LB/72245LB, 10 ns read/write cycle time designed to run off a 3.3V supply for exceptionally low power consumption. 5V input tolerant These devices are very high-speed, low-power First-In, First-Out (FIFO) IDT Standard or First Word Fall Through timing memories with clocked read and write controls. These FIFOs are applicable Single or double register-buffered Empty and Full flags for a wide variety of data buffering needs, such as optical disk controllers, Local Easily expandable in depth and width Area Networks (LANs), and interprocessor communication. Asynchronous or coincident Read and Write Clocks These FIFOs have 18-bit input and output ports. The input port is controlled Asynchronous or synchronous programmable Almost-Empty by a free-running clock (WCLK), and an input enable pin (WEN). Data is read and Almost-Full flags with default settings into the synchronous FIFO on every clock when WEN is asserted. The output Half-Full flag capability port is controlled by another clock pin (RCLK) and another enable pin (REN). Output enable puts output data bus in high-impedance state The Read Clock(RCLK) can be tied to the Write Clock for single clock operation High-performance submicron CMOS technology or the two clocks can run asynchronous of one another for dual-clock operation. Available in a 64-lead thin quad flatpack (TQFP/STQFP) An Output Enable pin (OE) is provided on the read port for three-state control of the output. FUNCTIONAL BLOCK DIAGRAM WCLK D0-D17 LD WEN INPUT REGISTER OFFSET REGISTER FF/IR PAF FLAG WRITE CONTROL EF/OR LOGIC LOGIC PAE RAM ARRAY HF/(WXO) 256 x 18, 512 x 18 1,024 x 18, 2,048 x 18 READ POINTER WRITE POINTER 4,096 x 18 FL READ CONTROL WXI LOGIC EXPANSION LOGIC (HF)/WXO RXI OUTPUT REGISTER RXO RESET LOGIC RS 4294 drw 01 OE RCLK REN Q0-Q17 IDT, IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc. MARCH 2018 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-4294/8TM COMMERCIAL AND INDUSTRIAL IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 TEMPERATURE RANGES operation, which consists of activating REN and enabling a rising RCLK edge, DESCRIPTION (CONTINUED) will shift the word from internal memory to the data output lines. The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready In FWFT mode, the first word written to an empty FIFO is clocked directly (EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags, to the data output lines after three transitions of the RCLK signal. A REN does Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the not have to be asserted for accessing the first word. programmable flags is controlled by a simple state machine, and is initiated by These devices are depth expandable using a Daisy-Chain technique or asserting the Load pin (LD). A Half-Full flag (HF) is available when the FIFO First Word Fall Through mode (FWFT). The XI and XO pins are used to expand is used in a single device configuration. the FIFOs. In depth expansion configuration, First Load (FL) is grounded on There are two possible timing modes of operation with these devices: IDT the first device and set to HIGH for all other devices in the Daisy Chain. Standard mode and First Word Fall-Through (FWFT) mode. The IDT72V205/72V215/72V225/72V235/72V245 are fabricated using In IDT Standard Mode, the first word written to an empty FIFO will not appear high-speed submicron CMOS technology. on the data output lines unless a specific read operation is performed. A read PIN CONFIGURATIONS PIN 1 D15 1 Q14 48 D14 2 Q13 47 D13 3 GND 46 D12 4 Q12 45 D11 5 Q11 44 D10 6 VCC 43 D9 7 Q10 42 D8 8 Q9 41 D7 9 GND 40 D6 10 Q8 39 D5 11 Q7 38 D4 12 Q6 37 D3 13 Q5 36 D2 14 GND 35 D1 15 Q4 34 D0 16 VCC 33 4294 drw 02 TQFP (PN64-1, order code: PF) STQFP (PP64-1, order code: TF) TOP VIEW 2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PAE D16 D17 FL WCLK GND WEN RCLK WXI REN VCC LD PAF OE RXI RS FF VCC WXO/HF GND EF RXO Q0 Q17 Q1 Q16 GND GND Q15 Q2 Q3 VCC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32