DATASHEET 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 CONFIDENTIAL IDT74SSTUBF32869A The IDT74SSTUBF32869A includes a parity checking Description function. The IDT74SSTUBF32869A accepts a parity bit from the memory controller at its input pin PARIN one or The IDT74SSTUBF32869A is 14-bit 1:2 registered buffer two cycles after the corresponding data input, compares it with parity, designed for 1.7 V to 1.9 V VDD operation. with the data received on the D-inputs and indicates on its All clock and data inputs are compatible with the JEDEC opendrain PTYERR pin (active low) whether a parity error standard for SSTL 18. The control inputs are LVCMOS. All has occurred. The number of cycles depends on the setting outputs are 1.8V CMOS drivers optimized to drive the of C1. DDR2 DIMM load. They provide 50% more dynamic driver When used as a single device, the C1 input is tied low. strength than the standard SSTU32864 outputs. When used in pairs, the C1 inputs is tied low for the first The IDT74SSTUBF32869A operates from a differential register (front) and the C1 input is tied high for the second clock (CLK and CLK). Data are registered at the crossing of register. When used as a single register, the PPO and CLK going high, and CLK going low. PTYERR signals are produced two clock cycles after the The device supports low-power standby operation. When corresponding data input. When used in pairs, the PTYERR the reset input (RESET) is low, the differential input signals of the first register are left floating. The PPO outputs receivers are disabled, and undriven (floating) data, clock of the first register are cascaded to the PARIN signas on the and reference voltage (VREF) inputs are allowed. In second register (back). The PPO and PTYERR signals of addition, when RESET is low all registers are reset, and all the second register are produced three clock cycles after outputs except PTYERR are forced low. The LVCMOS the corresponding data input. Parity implimentation and RESET input must always be held at a valid logic high or device wiring for single and dual die is described in the low level. diagram below. To ensure defined outputs from the register before a stable If an error occurs, and the PTYERR is driven low, it stays clock has been supplied, RESET must be held in the low low for two clock cycles or until RESET is driven low. The state during power up. DIMM-dependent signals (DCKE, DCS, CSR and DODT) are not included in the parity check computations. In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. All registers used on an individual DIMM must be of the Therefore, no timing relationship can be guaranteed same configuration, i.e single or dual die. between the two. When entering reset, the register will be Features cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, 14-bit 1:2 registered buffer with parity check functionality when coming out of reset, the register will become active Supports SSTL 18 JEDEC specification on data inputs quickly, relative to the time to enable the differential input and outputs receivers. IDT74SSTUBF32869A must ensure that the 50% more dynamic driver strength than standard outputs remain low as long as the data inputs are low, the SSTU32864 clock is stable during the time from the low-to-high Supports LVCMOS switching levels on C1 and RESET transition of RESET and the input receivers are fully inputs enabled. This will ensures that there are no glitches on the Low voltage operation: VDD = 1.7V to 1.9V output. Available in 150 BGA package The device monitors both DCS and CSR inputs and will gate the Qn, PPO (Paritial-Parity-Out) and PTYERR (Parity Error) Parity outputs from changing states when both DCS and CSR are high. If either DCS and CSR input is low, the Applications Qn, PPO and PTYERR outputs will function normally. The DDR2 Memory Modules RESET input has priority over the DCS and CSR controls and will force the Qn and PPO outputs low and the Provides complete DDR DIMM solution with ICS98ULPA877A or IDTCSPUA877A PTYERR high. Ideal for DDR2 667 and 800 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 1 IDT74SSTUBF32869A 7093/10 CONFIDENTIALIDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Parity Implementation and Device Wiring PTYERR, W1 PPO, W8 PPO, W4 PARIN, W4 Register 1 Register 2 PARIN (Front) (Back) NC, A11 NC, A8 NC, A4 NC, A8 Set C=0 for Register 1, and C=1 for Register 2 Block Diagram (CS Active) VREF 2 2 PPO 2 2 Q D PARITY GENERATOR PARIN 2 AND CHECKER PTYERR R Q1A Q D D1 Q1B R 11 (1) Q14A (1) Q D D14 (1) Q14B R QCSA DCS0 D Q QCSB R CSR QCKEA DCKE D Q QCKEB R QODTA DODT D Q QODTB R RESET CLK CLK NOTE: 1.This range does not include D1, D4, and D7, and their corresponding outputs. 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 2 IDT74SSTUBF32869A 7093/10 CONFIDENTIAL