SEL OUT Low Skew, Dual, Programmable 1-to-2 ICS854S204I Differential-to-LVDS, LVPECL Fanout Buffer DATA SHEET General Description Features The ICS854S204I is a low skew, high performance dual, Two programmable differential LVDS or LVPECL output banks programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer. Two differential clock input pairs The PCLKx, nPCLKx pairs can accept most standard differential PCLKx, nPCLKx pairs can accept the following differential input levels. With the selection of SEL OUT signal, outputs can be input levels: LVDS, LVPECL, SSTL, CML selected be to either LVDS or LVPECL levels. The ICS854S204I is Maximum output frequency: 3GHz characterized to operate from either a 2.5V or a 3.3V power supply. Translates any single ended input signal to LVDS levels with Guaranteed output and bank skew characteristics make the resistor bias on nPCLKx inputs ICS854S204I ideal for those clock distribution applications demanding well defined performance and repeatability. Output skew: 15ps (maximum) Bank skew: 15ps (maximum) Propagation delay: 500ps (maximum) Additive phase jitter, RMS: 0.15ps (typical) Power Supply Configuration Table Full 3.3V or 2.5V supply modes V = 3.3V DD -40C to 85C ambient operating temperature 3.3V Operation V = nc TAP Available in lead-free (RoHS 6) package V = 2.5V DD 2.5V Operation V = 2.5V TAP SEL OUT Function Table SEL OUT Output Level 0LVDS 1 LVPECL Block Diagram Pin Assignment V TAP nPCLKB PCLKA 1 16 Pulldown 2 PCLKB SEL OUT nPCLKA 15 QA0 QA0 3 14 QB0 Pulldown nQA0 nQA0 4 13 nQB0 CLKA Pullup QA1 5 12 QB1 nCLKA QA1 nQA1 6 11 nQB1 nQA1 VTAP 7 10 VDD GND 8 9 QB0 nQB0 Pulldown ICS854S204I CLKB Pullup nCLKB QB1 16-Lead TSSOP nQB1 4.4mm x 5.0mm x 0.925mm package body G Package Top View ICS854S204BGI REVISION B NOVEMBER 18, 2011 1 2011 Integrated Device Technology, Inc.ICS854S204I Data Sheet LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1 PCLKA Input Pulldown Non-inverting differential clock input. 2 nPCLKA Input Pullup Inverting differential clock input. 3, 4 QA0, nQA0 Output Differential output pair. LVDS or LVPECL interface levels. 5, 6 QA1, nQA1 Output Differential output pair. LVDS or LVPECL interface levels. Power supply pin. Tie to V for 2.5V operation. For 3.3V operation, do not DD 7V Power TAP connect. 8 GND Power Power supply ground. Output select pin. Selects between LVDS or LVPECL outputs. 9 SEL OUT Input Pulldown LVCMOS/LVTTL interface levels. Power Power supply pin. 10 V DD 11, 12 nQB1, QB1 Output Differential output pair. LVDS or LVPECL interface levels. 13, 14 nQB0, QB0 Output Differential output pair. LVDS or LVPECL interface levels. 15 PCLKB Input Pulldown Non-inverting differential clock input. 16 nPCLKB Input Pullup Inverting differential clock input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 1pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN Function Tables Table 3. Clock Input Function Table Inputs Outputs PCLKA or nPCLKA or PCLKB nPCLKB QA 0:1 , QB 0:1 nQA 0:1 , nQB 0:1 Input to Output Mode Polarity 0 1 LOW HIGH Differential to Differential Non Inverting 1 0 HIGH LOW Differential to Differential Non Inverting 0 Biased NOTE 1 LOW HIGH Single Ended to Differential Non Inverting 1 Biased NOTE 1 HIGH LOW Single Ended to Differential Non Inverting Biased NOTE 1 0 HIGH LOW Single Ended to Differential Inverting Biased NOTE 1 1 LOW HIGH Single Ended to Differential Inverting NOTE 1: Please refer to the Application Information, Wiring the Differential Input to Accept Single Ended Levels section. ICS854S204BGI REVISION B NOVEMBER 18, 2011 2 2011 Integrated Device Technology, Inc.