89HPES24NT6AG2 24-Lane 6-Port PCIe Gen2 Datasheet System Interconnect Switch Two BARs (BAR2 and BAR4) support look-up table based Device Overview address translation The 89HPES24NT6AG2 is a member of the IDT family of PCI 32 inbound and outbound doorbell registers Express switching solutions. The PES24NT6AG2 is a 24-lane, 6-port 4 inbound and outbound message registers system interconnect switch optimized for PCI Express Gen2 packet Supports up to 64 masters switching in high-performance applications, supporting multiple simulta- Unlimited number of outstanding transactions neous peer-to-peer traffic flows. Target applications include multi-host or Multicast intelligent I/O based systems where inter-domain communication is required, such as servers, storage, communications, and embedded Compliant with the PCI-SIG multicast systems. Supports 64 multicast groups Supports multicast across non-transparent port Features Multicast overlay mechanism support High Performance Non-Blocking Switch Architecture ECRC regeneration support 24-lane, 6-port PCIe switch with flexible port configuration Integrated Direct Memory Access (DMA) Controllers Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s Supports up to 2 DMA upstream ports, each with 2 DMA chan- Gen1 operation nels Delivers up to 24 GBps (192 Gbps) of switching capacity Supports 32-bit and 64-bit memory-to-memory transfers Supports 128 Bytes to 2 KB maximum payload size Fly-by translation provides reduced latency and increased Low latency cut-through architecture performance over buffered approach Supports one virtual channel and eight traffic classes Supports arbitrary source and destination address alignment Port Configurability Supports intra- as well as inter-partition data transfers using Six x4 ports the non-transparent endpoint Automatic per port link width negotiation Supports DMA transfers to multicast groups (x4 x2 x1) Linked list descriptor-based operation Crosslink support Flexible addressing modes Automatic lane reversal Linear addressing Per lane SerDes configuration Constant addressing De-emphasis Quality of Service (QoS) Receive equalization Port arbitration Drive strength Round robin Innovative Switch Partitioning Feature Request metering Supports up to 6 fully independent switch partitions IDT proprietary feature that balances bandwidth among Logically independent switches in the same device switch ports for maximum system throughput Configurable downstream port device numbering High performance switch core architecture Supports dynamic reconfiguration of switch partitions Combined Input Output Queued (CIOQ) switch architecture with large buffers Dynamic port reconfiguration downstream, upstream, non-transparent bridge Clocking Dynamic migration of ports between partitions Supports 100 MHz and 125 MHz reference clock frequencies Movable upstream port within and between switch partitions Flexible port clocking modes Non-Transparent Bridging (NTB) Support Common clock Supports up to 6 NT endpoints per switch, each endpoint can Non-common clock communicate with other switch partitions or external PCIe Local port clock with SSC (spread spectrum setting) and port domains or CPUs reference clock input 6 BARs per NT Endpoint Bar address translation All BARs support 32/64-bit base and limit address translation IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 34 December 17, 2013 2013 Integrated Device Technology, IncIDT 89HPES24NT6AG2 Datasheet Hot-Plug and Hot Swap 9 General Purpose I/O Hot-plug controller on all ports Test and Debug Hot-plug supported on all downstream switch ports Ability to inject AER errors simplifies in system error handling 2 software validation All ports support hot-plug using low-cost external I C I/O expanders On-chip link activity and status outputs available for several ports Configurable presence-detect supports card and cable appli- cations Per port link activity and status outputs available using 2 external I C I/O expander for all remaining ports GPE output pin for hot-plug event notification Enables SCI/SMI generation for legacy operating system Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG support Standards and Compatibility Hot-swap capable I/O PCI Express Base Specification 2.1 compliant Power Management Implements the following optional PCI Express features Supports D0, D3hot and D3 power management states Advanced Error Reporting (AER) on all ports Active State Power Management (ASPM) End-to-End CRC (ECRC) Supports L0, L0s, L1, L2/L3 Ready, and L3 link states Access Control Services (ACS) Configurable L0s and L1 entry timers allow performance/ Device Serial Number Enhanced Capability power-savings tuning Sub-System ID and Sub-System Vendor ID Capability SerDes power savings Internal Error Reporting Supports low swing / half-swing SerDes operation Multicast SerDes associated with unused ports are turned off VGA and ISA enable SerDes associated with unused lanes are placed in a low L0s and L1 ASPM power state ARI Reliability, Availability, and Serviceability (RAS) Power Supplies ECRC support Requires three power supply voltages (1.0V, 2.5V, and 3.3V) AER on all ports Packaged in a 23mm x 23mm 484-ball Flip Chip BGA with SECDED ECC protection on all internal RAMs 1mm ball spacing End-to-end data path parity protection Product Description Checksum Serial EEPROM content protected Ability to generate an interrupt (INTx or MSI) on link up/down With Non-Transparent Bridging functionality and innovative Switch transitions Partitioning feature, the PES24NT6AG2 allows true multi-host or multi- Initialization / Configuration processor communications in a single device. Integrated DMA control- Supports Root (BIOS, OS, or driver), Serial EEPROM, or lers enable high-performance system design by off-loading data transfer SMBus switch initialization operations across memories from the processors. Each lane is capable Common switch configurations are supported with pin strap- of 5 GT/s link speed in both directions and is fully compliant with PCI ping (no external components) Express Base Specification 2.1. Supports in-system Serial EEPROM initialization/program- A non-transparent bridge (NTB) is required when two PCI Express ming domains need to communicate to each other. The main function of the On-Die Temperature Sensor NTB block is to initialize and translate addresses and device IDs to Range of 0 to 127.5 degrees Celsius allow data exchange across PCI Express domains. The major function- Three programmable temperature thresholds with over and alities of the NTB block are summarized in Table 1. under temperature threshold alarms Automatic recording of maximum high or minimum low temperature 2 of 34 December 17, 2013