BBT3821LP-JH Renesas

BBT3821 Data Sheet July 20, 2005 FN7483.2 0.13mm Pure-Digital CMOS Technology Octal 2.488Gbps to 3.187Gbps/ Lane Retimer 1.5V Core Supply, Control I/O 2.5V Tolerant Clock Compensation Features Tx/Rx Rate Matching via IDLE Insertion/Deletion up to 8 Lanes of Clock & Data Recovery and Retiming 4 in 100ppm Clock Difference Each Direction Receive Signal Detect and 16 Levels of Receiver Differential Input/Output Equalization for Media Compensation Wide Operating Data Rate Range: 2.488Gbps to CML CX4 Transmission Output with 16 Settable Levels of 3.1875Gbps, and 1.244Gbps to 1.59325Gbps Pre-Emphasis, Eight on XAUI Side Ultra Low-Power Operation (195mW typical per lane, Single-Ended or Differential Input Lower-Speed Reference 1550mW typical total consumption) Clock Low Power Version Available for LX4 Applications Ease of Testing 17mm Square Low Profile 192 pin 1.0mm Pitch EBGA Complete Suite of Ingress-Egress Loopbacks Package Full 802.3ae Pattern Generation and Test, including Compliant to the IEEE 802.3 10GBASE-LX4(WWDM), CJPAT & CRPAT 10GBASE-CX4, and XAUI Specifications 23 PRBS (both 2 -1 and 13458 byte) Built-In Self Tests, Reset Jitter Domain Error Flags and Count Output Meets 802.3ae and 802.3ak Jitter Requirements with JTAG and AC-JTAG Boundary Scan Significant Margin Long Run Length (512 bit) Frequency Lock Ideal for Received Data Aligned to Local Reference Clock for Proprietary Encoding Schemes Retransmission Extensive Configuration and Status Reporting via 802.3 Increase Driving Distance Clause 45 Compliant MDC/MDIO Serial Interface LX4: Up to 40 inches of FR-4 Traces or 500 Meters of Automatic Load of BBT3821 Control and all XENPAK MMF Fiber at 3.1875Gbps Registers from EEPROM or DOM Circuit CX4: Over 15 meters of Compatible Cable Deskewing and Lane-to-Lane Alignment Figure 1. FUNCTIONAL BLOCK DIAGRAM Egress 3 Egress 2 Egress 1 Egress 0 Ingress 3 Ingress 2 Ingress 1 Ingress 0 Receive RX0N Parallel TX0N Deserializer Clock & 8B/10B 8B/10B Receive Data RX0P Data and Comma Encoder TX0P Decoder FIFO Recovery Detector & Mux MDIO MDC SCL SDA RFCP RFCN MDIO/MDC Clock Multiplier 2 I C Interface 3.125G Register File CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-352-6832 Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.BBT3821 Table of Contents Features 1 Table of Contents . 2 List of Figures 4 List of Tables 5 General Description . 9 Functions . 9 Receiver Operations . 9 Loss of Signal Detection, Termination & Equalization . 9 Clock and Data Recovery . 10 Byte Alignment (Code-Group Alignment) . 10 8b/10b Decoding . 10 Receive FIFO 10 Deskew (Lane to Lane) Alignment 10 Clock Compensation . 11 Transmitter Operations . 11 8b/10b Encoding 11 Pre-Emphasis 11 8b/10b Coding and Decoding 12 8 Bit Mode 12 10 Bit Mode . 13 Error Indications 13 Loss of Signal 13 Byte or Lane Synchronization Failure . 13 Channel Fault Indications 13 Coding Violation, Disparity & FIFO Errors . 13 Loopback Modes . 13 PMA Loopback (1.0.0 & 1.C004. 11:8 ) 13 PHY XS (Serial) Loopback (4.0.14 & 4.C004. 11:8 ) . 14 PCS Parallel Network Loopback (3.C004. 3:0 ) . 14 PCS (Parallel) Loopback (4.C004. 3:0 & Optionally 3.0.14) . 14 Serial Test Loopbacks (1.C004.12 & 4.C004.12) . 15 Serial Management Interface 15 MDIO Register Addressing 15 I2C Space Interface . 16 NVR Registers & EEPROM . 16 Auto-Configuring Control Registers . 16 DOM Registers . 16 General Purpose (GPIO) Pins . 17 LASI Registers & I/O 17 Reading Additional EEPROM Space Via the I2C Interface . 17 Writing EEPROM Space through the I2C Interface 19 2