DATASHEET 82C50A FN2958 Rev.6.00 CMOS Asynchronous August 19, 2015 CMOS Asynchronous Features The 82C50A Asynchronous Communication Element Single Chip UART/BRG (ACE) is a high performance programmable Universal DC to 625K Baud (DC to 10MHz Clock) Asynchronous Receiver/Transmitter (UART) and Baud Crystal or External Clock Input Rate Generator (BRG) on a single chip. Using Intersils advanced Scaled SAJI IV CMOS Process, the ACE will On Chip Baud Rate Generator 1 to 65535 Divisor support data rates from DC to 625K baud (0-10MHz clock). Generates 16X Clock The ACEs receiver circuitry converts start, data, stop, and Prioritized Interrupt Mode parity bits into a parallel data word. The transmitter circuitry Fully TTL/CMOS Compatible converts a parallel data word into serial form and appends Microprocessor Bus Oriented Interface the start, parity, and stop bits. The word length is programmable to 5, 6, 7, or 8 data bits. Stop bit selection 80C86/80C88 Compatible provides a choice of 1,1.5, or 2 stop bits. Scaled SAJI IV CMOS Process The Baud Rate Generator divides the clock by a divisor Low Power - 1mA/MHz Typical 16 programmable from 1 to 2 -1 to provide standard RS- 232C baud rates when using any one of three industry Modem Interface standard baud rate crystals (1.8432MHz, 2.4576MHz, or Line Break Generation and Detection 3.072MHz). A programmable buffered clock output Loopback and Echo Modes (BAUDOUT) provides either a buffered oscillator or 16X (16 times the data rate) baud rate clock for general purpose Doubled Buffered Transmitter and Receiver system use. Single 5V Supply To meet the system requirements of a CPU interfacing to Pb-Free Plus Anneal Available (RoHS Compliant) an asynchronous channel, the modem control signals RTS, CTS, DSR, DTR, RI, DCD are provided. Inputs and outputs have been designed with full TTL/CMOS compatibility in order to facilitate mixed TTL/NMOS/CMOS system design. FN2958 Rev.6.00 Page 1 of 25 August 19, 201582C50A Ordering Information PKG. 625K BAUD PART MARKING TEMP RANGE (C) PACKAGE DWG. CP82C50A-5 (No longer available, CP82C50A-5 0 to +70 40 Ld PDIP E40.6 recommended replacement: CS82C50A-5Z) CP82C50A-5Z (Note) (No longer CP82C50A-5Z 0 to +70 40 Ld PDIP (Pb-free) E40.6 available, recommended replacement: CS82C50A-5Z) CS82C50A-5Z CS82C50A-5Z 0 to +70 44 Ld PLCC N44.65 (Note) (Pb-free) CS82C50A-5Z96 CS82C50A-5Z 0 to +70 44 Ld PLCC Tape and Reel N44.65 (Note) (Pb-free) IS82C50A-5Z (Note) IS82C50A-5Z -40 to +85 44 Ld PLCC (Pb-free) N44.65 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Functional Diagram MICROPROCESSOR INTERFACE CSO 12 24 CSOUT CS1 13 23 DDIS CS2 14 INTERRUPT 30 INTRPT ADS 25 ENABLE, ID, & CONTROL A0 28 A1 27 UART A2 26 10 SIN RECEIVER MR 35 9 RCLK 15 BAUDOUT DISTR 22 DIVISOR LATCH LINE STATUS DISTR 21 16 XTAL1 AND BAUD RATE AND CONTROL GENERATOR 17 XTAL2 DOSTR 19 11 SOUT DOSTR 18 TRANSMITTER 32 RTS D0 1 MODEM 33 DTR D1 2 34 OUT1 D2 3 MODEM CONTROL D3 4 31 OUT2 D4 5 36 CTS D5 6 37 DSR D6 7 MODEM STATUS 38 DCD D7 8 39 RI FN2958 Rev.6.00 Page 2 of 25 August 19, 2015