DATASHEET EL4585 FN7175 Rev 4.00 Horizontal Genlock, 8FSC September 3, 2009 The EL4585 is a PLL (Phase Lock Loop) sub-system, Features designed for video applications and also suitable for general 36MHz, general purpose PLL purpose use up to 36MHz. In video applications, this device generates a TTL/CMOS-compatible pixel clock (CLK OUT) 8F timing (use the EL4584 for 4F ) SC SC which is a multiple of the TV horizontal scan rate and phase Compatible with EL4583 sync separator locked to it. VCXO, Xtal, or LC tank oscillator The reference signal is a horizontal sync signal, TTL/CMOS < 2ns jitter (VCXO) format, which can be easily derived from an analog composite video signal with the EL4583 sync separator. An User-controlled PLL capture and lock input signal to coast is provided for applications where Compatible with NTSC and PAL TV formats periodic disturbances are present in the reference video timing such as VTR head switching. The lock detector output 8 pre-programmed popular TV scan rate clock divisors indicates correct lock. Single 5V, low current operation The divider ratio is four ratios for NTSC and four similar Pb-Free Available (RoHS Compliant) ratios for the PAL video timing standards by external selection of three control pins. These four ratios have been Applications selected for common video applications including 8F , SC Pixel clock regeneration 6F , 27MHz (CCIR 601 format) and square picture SC elements used in some workstation graphics. To generate Video compression engine (MPEG) clock generator 4F , 3F , 13.5MHz (CCIR 601 format) etc., use the SC SC Video capture or digitization EL4584, which does not have the additional divide-by-two stage of the EL4585. PIP (Picture in Picture) timing generator Text or graphics overlay timing For applications where these frequencies are inappropriate or for general purpose PLL applications the internal divider Ordering Information can be bypassed and an external divider chain used. PART PART PKG. FREQUENCIES AND DIVISORS NUMBER MARKING PACKAGE DWG. 6F CCIR 601 SQUARE SC EL4585CN EL4585CN 16 Ld PDIP E16.3 FUNCTION (Note 1) (Note 2) (Note 3) 8F SC EL4585CS EL4585CS 16 Ld SOIC MDP0027 Divisor (Note 4) 1702 1728 1888 2270 EL4585CS-T7* EL4585CS 16 Ld SOIC MDP0027 PAL F (MHz) 26.602 27.0 29.5 35.468 EL4585CS-T13* EL4585CS 16 Ld SOIC MDP0027 OSC EL4585CSZ EL4585CSZ 16 Ld SOIC MDP0027 Divisor (Note 4) 1364 1716 1560 1820 (Note 5) (Pb-free) NTSC F (MHz) 21.476 27.0 24.546 28.636 OSC EL4585CSZ-T7* EL4585CSZ 16 Ld SOIC MDP0027 (Note 5) (Pb-free) NOTES: EL4585CSZ-T13* EL4585CSZ 16 Ld SOIC MDP0027 1. 6F frequencies do not yield integer divisors. SC (Note 5) (Pb-free) 2. CCIR 601 divisors yield 1440 pixels in the active portion of each *Please refer to TB347 for details on reel specifications. line for NTSC and PAL. NOTES: 3. Square pixels format gives 640 pixels for NTSC and 768 pixels 5. These Intersil Pb-free plastic packaged products employ special for PAL. Pb-free material sets, molding compounds/die attach materials, 4. Divisor does not include 2 block. and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 6. For 3F and 4F clock frequency operation, see EL4584 SC SC datasheet. Demo Board A demo PCB is available for this product. FN7175 Rev 4.00 Page 1 of 15 September 3, 2009EL4585 Pinout EL4585 (16 LD SOIC, PDIP) TOP VIEW PROG B 1 16 PROG A PROG C 2 15 CLK OUT OSC/VCO OUT 3 14 VSS (D) VDD (A) 4 13 EXT DIV OSC/VCO IN 5 12 LOCK DET VSS (A) 6 11 VDD (D) CHARGE PUMP OUT 7 10 HSYNC IN DIV SELECT 8 9 COAST FN7175 Rev 4.00 Page 2 of 15 September 3, 2009