DATASHEET HA-4900, HA-4902, HA-4905 FN2855 Rev 5.00 Precision Quad Comparators June 28, 2012 The HA-4900 series are monolithic, quad, precision Features comparators offering fast response time, low offset voltage, Fast Response Time 130ns low offset current and virtually no channel-to-channel crosstalk for applications requiring accurate, high speed, Low Offset Voltage . 2.0mV signal level detection. These comparators can sense signals Low Offset Current .10nA at ground level while being operated from either a single +5V Single or Dual Voltage Supply Operation supply (digital systems) or from dual supplies (analog networks) up to 15V. The HA-4900 series contains a Selectable Output Logic Levels unique current driven output stage which can be connected Active Pull-Up/Pull-Down Output Circuit. No External to logic system supplies (V + and V -) to make LOGIC LOGIC Resistors Required the output levels directly compatible (no external components needed) with any standard logic or special Pb-Free Plus Anneal Available (RoHS Compliant) system logic levels. In combination analog/digital systems, the design employed in the HA-4900 series input and output Applications stages prevents troublesome ground coupling of signals Threshold Detector between analog and digital portions of the system. Zero Crossing Detector These comparators combination of features make them ideal components for signal detection and processing in data Window Detector acquisition systems, test equipment and Analog Interfaces for Microprocessors microprocessor/analog signal interface networks. High Stability Oscillators For military grade product, refer to the HA-4902/883 data Logic System Interfaces sheet. Ordering Information Pinout HA-4900, HA-4902 (CERDIP) TEMP HA-4905 (PDIP, CERDIP, SOIC) PART PART RANGE PKG. o TOP VIEW NUMBER MARKING ( C) PACKAGE DWG. HA1-4900-2 HA1-4900-2 -55 to 125 16 Ld CERDIP F16.3 V + 1 16 OUT 4 L HA1-4902-2 HA1-4902-2 -55 to 125 16 Ld CERDIP F16.3 OUT 1 2 15 -IN 4 - 4 HA1-4905-5 HA1-4905-5 0 to 75 16 Ld CERDIP F16.3 + -IN 1 3 14 +IN 4 - 1 HA3-4905-5 HA3-4905-5 0 to 75 16 Ld PDIP E16.3 + +IN 1 4 13 V+ HA9P4905-5 HA9P4905-5 0 to 75 16 Ld SOIC M16.3 V- 5 12 +IN 3 + 3 - HA9P4905-5Z HA9P4905- 0 to 75 16 Ld SOIC M16.3 +IN 2 6 11 -IN 3 + (See Note) 5Z (Pb-free) 2 - -IN 2 7 10 OUT 3 NOTE: Intersil Pb-free plus anneal products employ special Pb-free OUT 2 8 9 V - L material sets molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN2855 Rev 5.00 Page 1 of 10 June 28, 2012HA-4900, HA-4902, HA-4905 Absolute Maximum Ratings Thermal Information o o Supply Voltage (Between V+ and V- Terminals) 33V Thermal Resistance (Typical, Note 3) ( C/W) ( C/W) JA JC Differential Input Voltage .15V CERDIP Package . 85 25 Voltage Between V + and V - 18V PDIP Package . 90 N/A LOGIC LOGIC Output Current . 50mA SOIC Package . 100 N/A o Power Dissipation (Notes 1, 2) Maximum Junction Temperature (Ceramic Package) .175 C o Maximum Junction Temperature (Plastic Package) 150 C o o Maximum Storage Temperature Range . -65 C to 150 C Operating Conditions o Maximum Lead Temperature (Soldering 10s) 300 C Temperature Range (SOIC - Lead Tips Only) o o HA-4900-2, HA-4902-2 . -55 C to 125 C o o HA-4905-5 0 C to 75 C Die Characteristics Back Side Potential V- Number of Transistors . 137 Die Size 95 mils x 105 mils CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: o 1. Maximum power dissipation, including output load, must be designed to maintain the junction temperature below 175 C for ceramic packages, o and below 150 C for plastic packages. 2. Total Power Dissipation (T.P.D.) is the sum of individual dissipation contributions of V+, V- and V shown in curves of Power Dissipation LOGIC vs Supply Voltages (see Performance Curves). The calculated T.P.D. is then located on the graph of Maximum Allowable Package Dissipation vs Ambient Temperature to determine ambient temperature operating limits imposed by the calculated T.P.D. (See Performance Curves). For instance, the combination of +15V, -15V, +5V, 0V (V+, V-, V +, V -) gives a T.P.D. of 350mW, the combination +15V, -15V, +15V, LOGIC LOGIC 0V gives a T.P.D. of 450mW. 3. is measured with the component mounted on an evaluation PC board in free air. JA Electrical Specifications V = 15V, V + = 5V, V - = GND SUPPLY LOGIC LOGIC HA-4900-2 HA-4902-2 HA-4905-5 o o o o o o -55 C to 125 C -55 C to 125 C 0 C to 75 C TEMP o PARAMETER ( C) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS INPUT CHARACTERISTICS Offset Voltage (Note 4) 25 - 2 3 - 2 5 - 4 7.5 mV Full - - 4 - - 8 - - 10 mV Offset Current 25 - 10 25 - 10 35 - 25 50 nA Full - - 35 - - 45 - - 70 nA Bias Current (Note 5) 25 - 50 75 - 50 150 - 100 150 nA Full - - 150 - - 200 - - 300 nA Input Sensitivity (Note 6) 25 - - V + -- V + -- V + mV IO IO IO 0.3 0.5 0.5 Full - - V + -- V + -- V + mV IO IO IO 0.4 0.6 0.7 Common Mode Range Full V- - (V+) - V- - (V+) - V- - (V+) - V 2.4 2.6 2.4 Differential Input Resistance 25 - 250 - - 250 - - 250 - M TRANSFER CHARACTERISTICS Large Signal Voltage Gain 25 - 400 - - 400 - - 400 - kV/V Response Time (t (0)) 25 - 130 200 - 130 200 - 130 200 ns PD (Note 7) Response Time (t (1)) 25 - 180 215 - 180 215 - 180 215 ns PD (Note 7) FN2855 Rev 5.00 Page 2 of 10 June 28, 2012