DATASHEET HFA3102 FN3635 Rev.5.00 Dual Long-Tailed Pair Transistor Array July 14, 2005 The HFA3102 is an all NPN transistor array configured as Features dual differential amplifiers with tail transistors. Based on High Gain-Bandwidth Product (f ) . 10GHz T Intersil bonded wafer UHF-1 SOI process, this array achieves very high f (10GHz) while maintaining excellent High Power Gain-Bandwidth Product 5GHz T h and V matching characteristics over temperature. FE BE High Current Gain (h ) . 70 FE Collector leakage currents are maintained to under 0.01nA. Noise Figure (Transistor) . 3.5dB Ordering Information Low Collector Leakage Current <0.01nA TEMP. PKG. Excellent h and V Matching FE BE PART NUMBER RANGE (C) PACKAGE DWG. Pin-to-Pin to UPA102G HFA3102B96 -40 to 85 14 Ld SOIC Tape M14.15 and Reel Pb-Free Plus Anneal Available (RoHS Compliant) HFA3102BZ -40 to 85 14 Ld SOIC M14.15 Applications (Note) (Pb-free) HFA3102BZ96 -40 to 85 14 Ld SOIC Tape M14.15 Single Balanced Mixers (Note) and Reel (Pb-free) Wide Band Amplification Stages NOTE: Intersil Pb-free plus anneal products employ special Pb-free Differential Amplifiers material sets molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and Multipliers compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow Automatic Gain Control Circuits temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Frequency Doublers, Tripplers Oscillators Pinout/Functional Diagram Constant Current Sources HFA3102 (SOIC) Wireless Communication Systems TOP VIEW Radio and Satellite Communications 14 13 12 11 10 9 8 Fiber Optic Signal Processing High Performance Instrumentation Q 6 Q Q 1 2 Q Q 4 5 Q 3 12 34 56 7 FN3635 Rev.5.00 Page 1 of 7 July 14, 2005HFA3102 Absolute Maximum Ratings T = 25C Thermal Information A V Collector to Emitter Voltage 8.0V Thermal Resistance (Typical, Note 1) (C/W) CEO JA V Collector to Base Voltage . 12.0V CBO SOIC Package . 128 V Emitter to Base Voltage 12.0V EBO Maximum Power Dissipation at 75 I , Collector Current .30mA C Any One Transistor .0.25W Maximum Junction Temperature (Die) 175C Operating Conditions Maximum Junction Temperature (Plastic Package) 150C Maximum Storage Temperature Range -65C to 150C Temperature Range -40C to 85C Maximum Lead Temperature (Soldering 10s) . 300C (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. is measured with the component mounted on an evaluation PC board in free air. JA Electrical Specifications T = 25C A (NOTE 2) ALL GRADES TEST SYMBOLS PARAMETER TEST CONDITIONS LEVEL MIN TYP MAX UNITS V Collector-to-Base Breakdown Voltage (Q , I = 100 A, I = 0 A 12 18 - V (BR)CBO 1 C E Q , Q , and Q ) 2 4 5 V Collector-to-Emitter Breakdown I = 100 A, I = 0 A 8 12 - V (BR)CEO C B Voltage (Q thru Q ) 1 6 V Emitter-to-Base Breakdown Voltage (Q I = 50 A, I = 0 A 5.5 6 - V (BR)EBO 3 E C and Q ) 6 I Collector Cutoff Current V = 5V, I = 0 A - 0.1 10 CBO CB E (Q , Q , Q , and Q ) 1 2 4 5 I Emitter Cutoff Current (Q and Q)V = 1V, I = 0 A - - 100 EBO 3 6 EB C h DC Current Gain (Q thru Q)I = 10mA, V = 3V A 40 70 - - FE 1 6 C CE C Collector-to-Base Capacitance V = 5V, f = 1MHz B - 300 - fF CB CB C Emitter-to-Base Capacitance V = 0, f = 1MHz B - 200 - fF EB EB f Current Gain-Bandwidth Product I = 10mA, V = 5V C - 10 - GHz T C CE f Power Gain-Bandwidth Product I = 10mA, V = 5V C - 5 - GHz MAX C CE G Available Gain at Minimum Noise Figure I = 3mA, f = 0.5GHz C - 17.5 - dB NFMIN C V = 3V CE f = 1.0GHz C - 12.4 - dB NF Minimum Noise Figure I = 3mA, f = 0.5GHz C - 1.8 - dB MIN C V = 3V CE f = 1.0GHz C - 2.1 - dB NF 50 Noise Figure I = 3mA, f = 0.5GHz C - 3.3 - dB 50 C V = 3V CE f = 1.0GHz C - 3.5 - dB h /h DC Current Gain Matching I = 10mA, V = 3V A 0.9 1.0 1.1 - FE1 FE2 C CE (Q and Q , Q and Q ) 1 2 4 5 V Input Offset Voltage (Q and Q ), I = 10mA, V = 3V A - 1.5 5 mV OS 1 2 C CE (Q and Q ) 4 5 I Input Offset Current (Q and Q ), I = 10mA, V = 3V A - 5 25 A OS 1 2 C CE (Q and Q ) 4 5 dV /dT Input Offset Voltage TC I = 10mA, V = 3V C - 0.5 - V/C OS C CE (Q and Q , Q and Q ) 1 2 4 5 I Collector-to-Collector Leakage V = 5V B - 0.01 - nA TRENCH- TEST (Pin 6, 7, 13, and 14) LEAKAGE NOTE: 2. Test Level: A. Production Tested B. Typical or Guaranteed Limit Based on Characterization C. Design Typical for Information Only FN3635 Rev.5.00 Page 2 of 7 July 14, 2005