DATASHEET HI5714 FN3973 Rev 6.00 8-Bit, 40/60/75/80 MSPS A/D Converter July 2004 The HI5714 is a high precision, monolithic, 8-bit, Analog-to- Features Digital Converter fabricated in Intersil advanced HBC10 Sampling Rate . 40/60/75/80 MSPS BiCMOS process. Low Power 325mW The HI5714 is optimized for a wide range of applications such as ultrasound imaging, mass storage, instrumentation, and video 7.65 ENOB at 4.43MHz digitizing, where accuracy and low power consumption are Overflow/Underflow Three-State TTL Output essential. The HI5714 is offered in 40 MSPS, 60 MSPS, and 75 Operates with Low Level AC Clock MSPS sample rates. Very Low Analog Input Capacitance The HI5714 delivers 0.4 LSB differential nonlinearity while consuming only 325mW power (Typical) at 75 MSPS. The No Buffer Amplifier Required digital inputs and outputs are TTL compatible, as well as No Sample and Hold Required allowing for a low-level sine wave clock input. TTL Compatible I/O Ordering Information Pin-Compatible to Philips TDA8714 TEMP. SAMPLING Pb-free Available PART RANGE FREQUENCY PKG. NUMBER (C) PACKAGE (MHz) DWG. Applications HI5714/4CB 0 to 70 24 Ld SOIC 40 M24.3 Video Digitizing HI5714/4CBZ 0 to 70 24 Ld SOIC 40 M24.3 QAM Demodulator (Note) (Pb-free) Digital Cable Setup Box HI5714/7CB-T 0 to 70 24 Ld SOIC 75 M24.3 Tape & Reel Tape Drive/Mass Storage HI5714/7CBZ-T 0 to 70 24 Ld SOIC 75 M24.3 Medical Ultrasound Imaging (Note) Tape & Reel Communication Systems (Pb-free) HI5714EVAL 25 Evaluation Board Pinout NOTE: Intersil Pb-free products employ special Pb-free material HI5714 (SOIC) sets molding compounds/die attach materials and 100% matte tin TOP VIEW plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL D1 1 24 D2 classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. D0 2 23 D3 NC 3 22 OE V 4 21 V RB CCO2 NC 5 20 OGND AGND 6 19 V CCO1 V 7 18 V CCA CCD 17 DGND V 8 IN V 9 16 CLK RT NC 10 15 D4 O/UF 11 14 D5 D7 12 13 D6 FN3973 Rev 6.00 Page 1 of 14 July 2004 NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tscHI5714 Functional Block Diagram V CLK V OE CCA CCD 7 16 18 22 CLOCK DRIVER V 9 RT D7 12 D6 13 D5 14 15 D4 V IN 8 ANALOG TO DIGITAL 23 D3 TTL OUTPUTS LATCHES CONVERTER 24 D2 1 D1 2 D0 V 4 RB V CCO1 19 V CCO2 21 OGND 20 O/UF 11 OVERFLOW/UNDERFLOW TTL OUTPUT LATCH 6 17 AGND DGND Typical Application Schematic +5VA 2 D0 16 1 CLOCK CLK D1 3.6V 24 + D2 - 0.1 9 23 V D3 RT 15 D4 4 1.3V V 14 RB + D5 - 0.1 13 22 D6 OE 12 D7 HI5714 11 O/UF V IN 8 + 19 V IN V - CCO 21 V CCO 18 V +5VD CCD 1nF 0.1 F 7 +5VA V 20 CCA OGND 1nF 0.1F 3 NC 5 17 NC DGND 10 6 NC AGND AGND DGND BNC 1nF and 0.1 F CAPS are placed as close to part as possible. NOTES: 1. Pin 5 should be connected to AGND and pins 3 and 10 to DGND to reduce noise coupling into the device. 2. Analog and Digital supplies should be separated and decoupled to reduce digital noise coupling into the analog supply. FN3973 Rev 6.00 Page 2 of 14 July 2004