HI5731
Data Sheet September 15, 2004 FN4070.9
12-Bit, 100MSPS, High Speed D/A Features
Converter
Pb-free Available as an Option
The HI5731 is a 12-bit, 100MSPS, D/A converter which is
Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 100MSPS
implemented in the Intersil BiCMOS 10V (HBC-10) process.
Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .650mW
Operating from +5V and -5.2V, the converter provides
-20.48mA of full scale output current and includes an input
Integral Linearity Error . . . . . . . . . . . . . . . . . . . . 0.75 LSB
data register and bandgap voltage reference. Low glitch
Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . . 3.0pV-s
energy and excellent frequency domain performance are
achieved using a segmented architecture. The digital inputs
TTL/CMOS Compatible Inputs
are TTL/CMOS compatible and translated internally to ECL.
Improved Hold Time. . . . . . . . . . . . . . . . . . . . . . . . 0.25ns
All internal logic is implemented in ECL to achieve high
switching speed with low noise. The addition of laser Excellent Spurious Free Dynamic Range
trimming assures 12-bit linearity is maintained along the
Applications
entire transfer curve.
Cellular Base Stations
Ordering Information
GSM Base Stations
TEMP. PKG. DWG.
Wireless Communications
PART NUMBER RANGE (C) PACKAGE #
Direct Digital Frequency Synthesis
HI5731BIP -40 to 85 28 Ld PDIP E28.6
HI5731BIPZ -40 to 85 28 Ld PDIP E28.6
Signal Reconstruction
(See Note) (Pb-free)
Test Equipment
HI5731BIB -40 to 85 28 Ld SOIC M28.3
High Resolution Imaging Systems
HI5731BIB-T 28 Ld SOIC Tape and Reel M28.3
Arbitrary Waveform Generators
HI5731BIBZ -40 to 85 28 Ld SOIC M28.3
(See Note) (Pb-free)
Pinout
HI5731-EVS 25 Evaluation Board (SOIC)
HI5731
(PDIP, SOIC)
NOTE: Intersil Pb-free products employ special Pb-free material
TOP VIEW
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
D11 (MSB) 1 28 DGND
classified at Pb-free peak reflow temperatures that meet or exceed
D10 2 27 AGND
the Pb-free requirements of IPC/JEDEC J STD-020C.
D9 3 26 REF OUT
25 CTRL OUT
D8 4
D7 5 24 CTRL IN
D6 6 23 R
SET
D5 7 22 AV
EE
D4 8 21 I
OUT
D3 9 20 I
OUT
D2 10 19 ARTN
18
D1 11 DV
EE
D0 (LSB) 12 17 DGND
NC 13 16 DV
CC
NC 14 15 CLOCK
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright Intersil Americas Inc. 2002, 2004. All Rights ReservedHI5731
Typical Application Circuit
+5V
HI5731
0.01F
DV (16)
CC
D11 (MSB) (1)
D11
D10 (2)
D10 0.1F
(24) CTRL IN
D9 (3)
D9
(25) CTRL OUT
D8 (4)
D8
-5.2V (AV )
EE
D7 (5)
D7
(26) REF OUT
D6 D6 (6)
D5 D5 (7)
D/A OUT
(21) I
OUT
D4 D4 (8) 64
D3
D3 (9)
64
D2 D2 (10)
(20) I
OUT
D1
D1 (11)
(23) R
SET
D0 (LSB) (12)
D0
976
(19) ARTN
CLK (15)
(27) AGND
50
DGND (17, 28)
(22) AV
DV (18) EE
EE
0.01F
0.1F
0.01F
0.1F
- 5.2V (DV ) - 5.2V (AV )
EE
EE
Functional Block Diagram
(LSB) D0
D1
D2
D3
8 LSBs
R2R
CURRENT NETWORK
D4
CELLS
DATA
12-BIT
D5
BUFFER/
ARTN
SLAVE
MASTER
LEVEL
REGISTER REGISTER
D6
SHIFTER
227 227
D7
D8
15 15
15
D9
UPPER
SWITCHED
4-BIT
CURRENT
D10
DECODER
CELLS
I
OUT
(MSB) D11
I
OUT
REF CELL
CTRL
CLK
IN
25
+
OVERDRIVEABLE
CTRL
-
VOLTAGE OUT
REFERENCE
AV AGND DV DGND DV REF OUT R
EE EE CC SET
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