80C286 High Performance Microprocessor January 28, 2008 with Memory Management and Protection Features Description Compatible with NMOS 80286 The Intersil 80C286 is a static CMOS version of the NMOS Wide Range of Clock Rates 80286 microprocessor. The 80C286 is an advanced, high- - DC to 25MHz (80C286-25) performance microprocessor with specially optimized capa- - DC to 20MHz (80C286-20) bilities for multiple user and multi-tasking systems. The - DC to 16MHz (80C286-16) 80C286 has built-in memory protection that supports operat- - DC to 12.5MHz (80C286-12) ing system and task isolation as well as program and data - DC to 10MHz (80C286-10) privacy within tasks. A 25MHz 80C286 provides up to nine- Static CMOS Design for Low Power Operation teen times the throughput of a standard 5MHz 8086. The - ICCSB = 5mA Maximum 80C286 includes memory management capabilities that map - ICCOP = 185mA Maximum (80C286-10) 30 24 2 (one gigabyte) of virtual address space per task into 2 220mA Maximum (80C286-12) bytes (16 megabytes) of physical memory. 260mA Maximum (80C286-16) 310mA Maximum (80C286-20) The 80C286 is upwardly compatible with 80C86 and 80C88 410mA Maximum (80C286-25) software (the 80C286 instruction set is a superset of the High Performance Processor (Up to 19 Times the 8086 80C86/80C88 instruction set). Using the 80C286 real Throughput) address mode, the 80C286 is object code compatible with Large Address Space existing 80C86 and 80C88 software. In protected virtual 16 Megabytes Physical/1 Gigabyte Virtual per Task address mode, the 80C286 is source code compatible with Integrated Memory Management, Four-Level Memory 80C86 and 80C88 software but may require upgrading to Protection and Support for Virtual Memory and Operat- use virtual address as supported by the 80C286s integrated ing Systems memory management and protection mechanism. Both Two 80C86 Upward Compatible Operating Modes modes operate at full 80C286 performance and execute a - 80C286 Real Address Mode superset of the 80C86 and 80C88 instructions. - PVAM The 80C286 provides special operations to support the effi- Compatible with 80287 Numeric Data Co-Processor cient implementation and execution of operating systems. High Bandwidth Bus Interface (25 Megabyte/Sec) For example, one instruction can end execution of one task, Available In save its state, switch to a new task, load its state, and start - 68 Pin PGA (Commercial, Industrial, and Military) execution of the new task. The 80C286 also supports virtual - 68 Pin PLCC (Commercial and Industrial) memory systems by providing a segment-not-present excep- tion and restartable instructions. Ordering Information PACKAGE TEMP. RANGE 10MHz 12.5MHz 16MHz 20MHz 25MHz PKG. NO. o o PGA 0 C to +70 C - CG80C286-12 CG80C286-16 CG80C286-20 - G68.B o o -40 C to +85 C IG80C286-10 IG80C286-12 - - - G68.B o o -55 C to +125 C 5962- 5962- --- G68.B 9067801MXC 9067802MXC o o PLCC 0 C to +70 C - CS80C286-12 CS80C286-16 CS80C286-20 CS80C286-25 N68.95 o o -40 C to +85 C IS80C286-10 IS80C286-12 IS80C286-16 IS80C286-20 - N68.95 CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. FN2947.3 1-888-INTERSIL or 1-888-468-3774 Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003-2008. All Rights Reserved 1 All other trademarks mentioned are the property of their respective owners.80C286 Pinouts 68 LEAD PGA Component Pad View - As viewed from underside of the component when mounted on the board. 35 37 39 41 43 45 47 49 51 A0 D0 ERROR NC 34 36 38 40 42 44 46 48 50 53 52 A2 A1 NC BUSY 32 33 55 54 V CLK INTR NC CC 30 31 57 56 A3 RESET NMI NC 28 29 59 58 A5 A4 PEREQ V 26 27 61 60 SS A7 A6 READY V 24 25 63 62 CC A8 HLDA HOLD A9 22 23 65 64 A11 A10 20 21 67 66 M/IO COD/INTA 4 2 A13 A12 18 19 16 14 12 10 8 6 68 NC LOCK 3 1 17 15 13 11 9 7 5 PIN 1 INDICATOR 68 LEAD PGA P.C. Board View - As viewed from the component side of the P.C. board. 51 49 47 45 43 41 39 37 35 NC ERROR D0 A0 52 53 50 48 46 44 42 40 38 36 34 BUSY NC A1 A2 54 55 33 32 NC INTR CLK V 56 57 31 30 CC NC NMI RESET A3 58 59 29 28 V PEREQ A4 A5 60 61 27 26 SS V READY A6 A7 62 63 25 24 CC HOLD HLDA 64 65 23 22 A8 A9 COD/INTA M/IO 66 67 21 20 A10 A11 68 2 4 68 10 12 14 16 19 18 LOCK NC A12 A13 13 579 11 13 15 17 PIN 1 INDICATOR 2 A14 A12 V D0 SS A16 A15 D1 D8 BHE NC ERROR D15 A18 A17 D2 D9 NC S1 D7 D14 A20 A19 D3 D10 S0 PEACK D6 D13 V A21 D4 D11 SS A23 A22 D5 D12 A23 A22 D5 D12 V A21 D4 D11 SS S0 PEACK D6 D13 A20 A19 D3 D10 NC S1 D7 D14 A18 A17 D2 D9 BHE NC ERROR D15 A16 A15 D1 D8 A14 A12 D0 V SS