USERS MANUAL ISL1904DEMO1Z AN1845 Rev 0.00 Demonstration Board Aug 28, 2013 Introduction Design Specifications The ISL1904DEMO1Z demo board converts a high line AC Input voltage V : 176V to 264V IN input voltage to a 18V, 700mA DC output. It is implemented Output voltage V : 12V to 20V O with Intersils critical conduction mode (CrCM) LED driver Output current I : 700mA (14W) O controller, the ISL1904. It demonstrates the fundamental 3 functions of ISL1904, including soft-start, dimming, Board dimensions: 682615mm (LWH) over-voltage protection, short circuit protection, etc. The circuit Input power factor greater than 0.93 at nominal operates in CrCM with variable frequency and allows near Total harmonic distortion less than 7% at nominal zero-voltage switching (ZVS). Typical efficiency is about 81% at full load. The ISL1904DEMO1Z demo board supports phase Peak efficiency at full load: 81% dimming and is compatible with wide variety of leading and 0-100% flicker free dimming with leading and trailing edge trailing edge dimmers available in the market. This application dimmers note covers the performance data, critical waveforms, extensive dimming data, schematics, layout and bill of materials. 1200mH 18V, 660mA PA2517NL LED + D15 L5 T1 LED Driver with Triac Dimming 300V, 2A PDS3200-13-T JP2 10mH, 0.13A R9 220k 1206 400 O Cclamp RES 100 Rclamp LINE R4 L2 R7 DNP Cout1 LED R36 DNP 10O 600V, 0.5A Load 10mH 400 O MB6S 25V 25V RES100 Dclamp JP1 680F, 20% 680F, 20% R8 R39 DNP 25V C14 D1 R1 1F, 10% L1 220k + 499k C10 C28 1206 450V 1206 ac1 C34 10 O 176V-264V, 330nF, 10% Q2 0603 ~ ~ 450V 2SK3471 50Hz 47nF, 47nF, 100nF, 10% 400V 400V 5.4mH G R34 R2 102 O Vdrain 680 LED - 499k 1206 2512 10O 1206 R17 0805 BAV70 650V, 7A 70V, 0.2A 400V TK5P60V D14 C20 2200pF, 20% D2 NEUTRAL 21.5k R10 Q1 R29 13V 0603 Zener DHC R30 D10 R33 499O 300O R41 1.5O 0603 MCL4448 1.3O 2512 1206 1206 1.58k MCL4448 G 0603 D18 R44 D16 50V 600V 100pF, 5% 47k 1A R37 R38 0603 C18 4.99k DNP 0603 0603 C33 Q3 500V 16V 2Meg 0.38A 1 VDD OUT 16 R14 100nF, 10% 0805 2 OFFREF PWMOUT 15 NC 3 14 VREF DHC DHC ISL1904DEMO1Z Rev D 4 IOUT GND 13 ac1 R19 5 CS+ AC 12 R40 510k 6 OC 11 OVP DNP 0603 7 FB RAMP 10 C6 8 DELADJ VERR 9 R21 4.99k 16V ISL1904 DNP 0603 100nF, 10% R20 C12 91k C17 R15 C31 R13 R3 R22 0603 C5 C30 51k C4 C2 R16 0603 1k C29 16V 50V 16V 0603 0.1F, 10% 1000pF, 5% 0.1F, 10% 25V 25V 50V 90k 4.02k 33F, 20% 100pF, 5% 220F, 20% 0603 0603 FIGURE 1. ISOLATED FLYBACK CONVERTER APPLICATION SCHEMATIC ISL1904DEMO1ZD ISL1904DEMO1ZD LINE LINE LED Driver LED Driver Dimmer LED + LED + LED LED V V AC LINE OUT OUT VIN LOAD AC LINE V LOAD IN LED - LED - NEUTRAL NEUTRAL FIGURE 2. TEST SETUP WITH AND WITHOUT DIMMING AN1845 Rev 0.00 Page 1 of 18 Aug 28, 2013 Rsense Rsense1 Cout2 Cout3ISL1904DEMO1Z FIGURE 3. TOP/BOTTOM VIEW OF THE EVALUATION BOARD voltage reaches a minimum value to allow quasi-ZVS (Zero Schematic Description Voltage Switching) operation. Resistor R16 to ground programs the delay. General Description of ISL1904 The ISL1904 is a high-performance, critical conduction mode DELAY TIME SETTING (CrCM), single-ended flyback LED driver controller. It supports In order to reduce electromagnetic interference and switching single-stage conversion of the AC mains to a constant current loss, ISL1904 can insert a delay between the off period and the source with power factor correction (PFC). It also may be used on period. A resistor connected from deladj pin to ground will with DC input converters. The ISL1904 also supports boost, Cuk, program the delay time according to the equation below. The sepic and buck-boost converters. Operation in CrCM allows near optimal delay time depends on the resonance between the zero-voltage switching (ZVS) for improved efficiency while inductance, drain-source capacitance (Coss) and parasitic maximizing magnetic core utilization. The ISL1904 LED driver capacitance on the drain node. Circuit designers should optimize provides all of the features required for high-performance the delay according to the following equation: dimmable LED driver designs. 1 ----------------------------------------------------------------- fsw = 2 LpCoss + Cstray Input EMI Filtering After determining the delay time, the resistor can be chosen Fusible resistor R4 provides protection from components failure. according to the following equation: Input EMI filtering is provided by differential inductors L2, L5 and Tdel 73.33 Rdel = k capacitors C14 and C28. The switching current generated by the -------------------------------------- 10.2 power-train to the AC line is filtered by the input filter network. Resistor R16 programs this delay in the application schematic. Start-up Network Feedback A linear regulator startup network is used for initial startup. R7, The ISL1904 is designed to regulate the LED current by R8, R9, R36, Q2 and D2 constitute the linear startup circuit. monitoring the primary switch current at the OC pin through Once the energy is built and voltage is generated on the aux resistors Rsense and Rsense1. The peak primary switch current winding, the linear regulator circuit is disabled and the aux is captured, processed, and output on I as a PWM voltage OUT winding supplies the voltage and current to the controller IC. signal modulated in proportion to the LED current. The I PWM OUT frequency is the same as the converter switching frequency and Power Stage its amplitude is equivalent to 4x the peak switch current during The primary current loop encompasses the transformer primary the previous ON-time. Resistor R19 scales the signal before winding, MOSFET Q1 and the current sense resistors Rsense and being input to the control loop at the FB pin. The OC pin also Rsense1. provides cycle-by-cycle overcurrent protection. The ON-time is terminated if OC exceeds 0.6V nominal. There is ~120ns of Near zero voltage switching (ZVS) or quasi-resonant switching, as leading edge blanking (LEB) on OC to minimize or eliminate it is sometimes referred to, can be achieved by delaying the next external filtering. switching cycle after the inductor current decays to zero. The delay allows the inductance and parasitic capacitance to Output Rectification oscillate, causing the switching FET drain-source voltage to ring Transformer secondary winding voltage is rectified by diode D15 down to minima. If the FET is turned on at this minima, the 1 2 --- and filtered by capacitors Cout1, Cout2 and Cout3. The capacitive switching losses CV are greatly reduced. 2 capacitors are connected in parallel as the combination has a Inductor zero-crossing is detected using the transformer aux lower parasitic inductance and resistance compared to a single winding. R29, R12 scales down the sensed zero crossing voltage capacitor. and is delivered to the IC. Deladj sets the delay before a new switching cycles starts. This adjustment allows the user to delay the next switching cycle until the switching FET drain-source AN1845 Rev 0.00 Page 2 of 18 Aug 28, 2013