DATASHEET ISL22346 FN6177 Rev 2.00 2 Quad Digitally Controlled Potentiometers (XDCP) Low Noise, Low Power I C September 3, 2009 Bus, 128 Taps The ISL22346 integrates four digitally controlled potentiometers Features (DCP) and non-volatile memory on a monolithic CMOS Four potentiometers in one package integrated circuit. 128 resistor taps The digitally controlled potentiometers are implemented with 2 a combination of resistor elements and CMOS switches. The I C serial interface position of the wipers are controlled by the user through the - Three address pins, up to eight devices/bus 2 I C bus interface. Each potentiometer has an associated Non-volatile storage of wiper position volatile Wiper Register (WR) and a non-volatile Initial Value Wiper resistance: 70 typical V = 3.3V Register (IVR) that can be directly written to and read by the CC user. The contents of the WR controls the position of the Shutdown mode wiper. At power-up the device recalls the contents of the two Shutdown current 5A max DCPs IVR to the corresponding WRs. Power supply: 2.7V to 5.5V The DCPs can be used as a three-terminal potentiometers or as a two-terminal variable resistors in a wide variety of 50kor 10k total resistance applications including control, parameter adjustments, and High reliability signal processing. - Endurance: 1,000,000 data changes per bit per register - Register data retention: 50 years T < +55C 20 Ld TSSOP or 20 Ld TQFN package Pb-free (RoHS compliant) Pinouts ISL22346 ISL22346 (20 LD TSSOP) (20 LD TQFN) TOP VIEW TOP VIEW RH3 1 20 RW0 RL3 2 19 RL0 O 20 19 18 17 16 RW3 3 18 RH0 RH1 1 15 RL0 A2 4 17 SHDN RL1 RW0 2 14 SCL 5 16 VCC 3 13 RW1 RH3 SDA 6 15 A1 4 RL3 12 RH2 GND 7 14 A0 RW3 5 11 RL2 RW2 8 13 RH1 RL2 9 12 RL1 6 7 8 9 10 RH2 10 11 RW1 FN6177 Rev 2.00 Page 1 of 16 September 3, 2009 RH0 A2 SCL SHDN SDA VCC GND A1 RW2 A0ISL22346 Ordering Information PART NUMBER PART RESISTANCE OPTION TEMP. RANGE PACKAGE PKG. (Note) MARKING (k ) (C) (Pb-free) DWG. ISL22346UFV20Z* 22346 UFVZ 50 -40 to +125 20 Ld TSSOP M20.173 ISL22346UFRT20Z* 223 46UFZ 50 -40 to +125 20 Ld 4x4 TQFN L20.4x4A ISL22346WFV20Z* 22346 WFVZ 10 -40 to +125 20 Ld TSSOP M20.173 ISL22346WFRT20Z* 223 46WFZ 10 -40 to +125 20 Ld 4x4 TQFN L20.4x4A *Add -TK suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Block Diagram V CC RH3 WR3 SCL RW3 POWER-UP RL3 SDA INTERFACE, 2 I C RH2 CONTROL A0 INTERFACE AND STATUS WR2 A1 RW2 LOGIC A2 RL2 RH1 WR1 RW1 NON- RL1 VOLATILE RH0 SHDN REGISTERS WR0 RW0 RL0 GND Pin Descriptions TSSOP PIN TQFN PIN NUMBER NUMBER PIN NAME DESCRIPTION 1 3 RH3 High terminal of DCP3 2 4 RL3 Low terminal of DCP3 3 5 RW3 Wiper terminal of DCP3 2 4 6 A2 Device address input for the I C interface 2 5 7 SCL Open drain I C interface clock input 2 6 8 SDA Open drain Serial data I/O for the I C interface 7 9 GND Device ground pin 8 10 RW2 Wiper terminal of DCP2 9 11 RL2 Low terminal of DCP2 10 12 RH2 High terminal of DCP2 11 13 RW1 Wiper terminal of DCP1 12 14 RL1 Low terminal of DCP1 13 15 RH1 High terminal of DCP1 2 14 16 A0 Device address input for the I C interface FN6177 Rev 2.00 Page 2 of 16 September 3, 2009