USERS MANUAL ISL55100A/BEVAL3/3Z AN1217 Rev 1.00 Evaluation Board Users Guide Sep 12, 2008 ISL55100 Device Application Overview The ISL55100 is a Quad Driver/Receiver device that is typically utilized in bi-directional testing applications where formatted timing sets write data to and read data back from digital devices. Examples of bi-directional bus based devices are UARTs, Real Time Clocks, Interrupt Controllers, Parallel I/O devices, FPGA s and others. Memory devices are also bi-directional in that data can be stored in them and then retrieved at a later time. The ISL55100 provides four driver/receiver pairs (DOUT0-3/VINP0-3) that are usually tied together in order to support bi-directional communications (bus cycle emulation). HIZ control of the drivers enables this configuration. FIGURE 2. DEVICE AREA, ISL55100A/BEVAL3/3Z EVALUATION BOARD 1 The ISL55100A/BEVAL3/3Z Evaluation Board enables easy DATA+0 2 access to the various ISL55100 connections. All inputs and outputs DATA-0 LOW HIGH MINI MAX0 DOUT0 72 52 DRIVER RAILS are matched for signal path length. THRESHOLDS /DRV EN+0 RCVR 71 . /DRV EN-0 22 VINP0 7 DATA+1 8 QUAD - WIDE RANGE, LOW ROUT, TRI-STATABLE - DRIVERS DATA-1 5 48 DOUT1 /DRV EN+1 6 VH(0-3) /DRV EN-1 29 VINP1 13 DATA+2 ISL55100 DATA+(0-3) 14 DOUT(0-3) DATA-2 + 11 44 - DOUT2 /DRV EN+2 DATA-(0-3) 12 /DRV EN-2 VL(0-3) 32 VINP2 19 DRV EN+(0-3) DATA+3 20 DATA-3 + VCC 27, 59, 61, 67 - 17 VEE 26, 60, 62, 68 40 DOUT3 /DRV EN+3 DRV EN-(0-3) 18 /DRV EN-3 36 VINP3 COMPARATOR OUTPUTS QUAD - DUAL LEVEL COMPARATOR - RECEIVERS 3737 /LOWSWING BITS 0- 3 2424 COMP OUT HIGH RAIL V CC 25 COMP HIGH COMP OUT LOW RAIL QA(0-3) CVA(0-3) COMP LOW V EE FIGURE 1. FUNCTIONAL ISL55100A/BEVAL3/3Z PINOUT VINP(0-3) V CC COMP HIGH The ISL55100 provides the means of translating the DUT s QB(0-3) bus levels for a test system (Figure 3). Level translation on CVB(0-3) COMP LOW Write Operations is accomplished with the drivers. Read V EE Operation level translation is done via the FIGURE 3. DIAGRAM OF ISL55100A/BEVAL3/3Z DRIVERS receiver/comparators. Comparator QA/QB outputs adjust AND RECEIVERS their levels to the tester side logic levels by way of the COMP-HIGH and COMP-LOW levels. Comparators in the The ISL55100A/BEVAL3/3Z is made up of four drivers and four dual level receivers. Drivers provide voltage level translation for Write receivers set the DUT side level thresholds. Further the operations while the Dual Level Comparators translate voltage Window Comparators (Dual Threshold Receivers) enable levels for Read operations. received data to be verified for proper levels (Valid1, Valid 0). Level translation enables the Pin Electronics Pattern Devices to write data to and read data back from different types of logic families. AN1217 Rev 1.00 Page 1 of 12 Sep 12, 2008 50 VL0 46 VL1 42 VL2 70 38 VL3 QA0 69 QB0 53 VH0 3 49 VH1 QA1 4 45 VH2 QB1 41 VH3 9 QA2 10 QB2 15 23 CVB0 QA3 16 30 CVB1 QB3 33 CVB2 35 CVB3 21 CVA0 28 CVA1 54 31 CVA2 VEXT 34 CVA3 26 VEE 27 VCCISL55100A/BEVAL3/3Z Basic Design Fundamentals Include: ISL55100A/BEVAL3/3Z Evaluation Board Matched circuit lengths on DATA inputs, Driver Outputs The ISL55100A/BEVAL3/3Z Evaluation board provides the and Comparator measurement points. means to experiment with an Intersil ISL55100A/BEVAL3/3Z Quad Driver Receiver. Experiments typically include Driver Banana jack terminals used for low frequency Waveform analysis based on the user s load. Driver analysis connections. (Power supplies, VDIGC/D Bias Busses) may also include waveforms at various voltage rails and also BNC connectors for high frequency connections. (Driver include data propagation and HIZ transition timing. data and enable inputs, driver outputs, receiver inputs, comparator outputs) The user can also collect information related to receiver comparator characteristics, device dynamic power Jumpers for static mode selections. (LowSwing, consumption and the timing of comparator outputs. In Differential Biasing, VEXT) addition, the evaluation board accommodates loop-back loads to All DATA, DRV EN and VINP signals have 50 testing and exercising of the LowSwing and VEXT modes of ground and may be jumpered to test busses via jumpers. operation. The DOUT LOAD and VDIGC/D busses on the ISL55100A/BEVAL3/3Z Evaluation board provide the user with flexibility to initiate special analysis. This document sets up the ISL55100A/BEVAL3/3Z in a typical usage/configuration. As the user progresses in knowledge, the concept behind the analysis capability of the DOUT LOAD, VDIGC and VDIGD should become evident. FIGURE 5. HIGH SPEED, TESTER SIDE, DRIVER CONNECTIONS There are six high speed BNC tester side connections for each of the four channels: DATA control the high/low activity. DRV EN enable/disable the driver outputs and QA/QB are receiver/window comparator outputs. FIGURE 6. LOW FREQUENCY CONNECTORS FIGURE 4. ISL55100A/BEVAL3/3Z EVALUATION BOARD COMP HIGH and LOW, CVA, CVB, V , V , GND and EE CC VDIGC/D are low frequency power supply banana jack BNCs are used for high frequency connections. Banana plugs connections. and jumpers are used for low frequency/power supply connections. AN1217 Rev 1.00 Page 2 of 12 Sep 12, 2008