DATASHEET ISL55110, ISL55111 FN6228 Rev 8.00 Dual, High Speed MOSFET Driver January 29, 2015 The ISL55110 and ISL55111 are dual high speed MOSFET Features drivers intended for applications requiring accurate pulse 5V to 12V pulse amplitude generation and buffering. Target applications include ultrasound, CCD imaging, piezoelectric distance sensing and High current drive 3.5A clock generation circuits. 6ns minimum pulse width With a wide output voltage range and low ON-resistance, these 1.5ns rise and fall times, 100pF load devices can drive a variety of resistive and capacitive loads Low skew with fast rise and fall times, allowing high-speed operation with low skew, as required in large CCD array imaging 3.3V and 5V logic compatible applications. In-phase (ISL55110) and anti-phase outputs (ISL55111) The ISL55110, ISL55111 are compatible with 3.3V and 5V Small QFN and TSSOP packaging logic families and incorporate tightly controlled input Low quiescent current thresholds to minimize the effect of input rise time on output pulse width. The ISL55110 has a pair of in-phase drivers while Pb-free (RoHS compliant) the ISL55111 has two drivers operating in anti-phase. Applications ISL55110 and ISL55111 have a power-down mode for low Ultrasound MOSFET driver power consumption during equipment standby times, making it ideal for portable products. CCD array horizontal driver The ISL55110 and ISL55111 are available in 16 Ld Exposed Clock driver circuits pad QFN packaging and 8 Ld TSSOP. Both devices are specified for operation over the full -40C to +85C Related Literature temperature range. AN1283, ISL55110 11EVAL1Z, ISL55110 11EVAL2Z Evaluation Board User s Manual ISL55110 AND ISL55111 DUAL DRIVER o VDD VH oo IN-A OA o o o ENABLE-QFN* OB IN-B o o ** GND o PD o *ENABLE AVAILABLE IN QFN PACKAGE ONLY **ISL55111 IN-B IS INVERTING FIGURE 1. FUNCTIONAL BLOCK DIAGRAM FN6228 Rev 8.00 Page 1 of 18 January 29, 2015ISL55110, ISL55111 Pin Configurations ISL55110 ISL55111 (16 LD QFN) (16 LD QFN) TOP VIEW TOP VIEW 16 15 14 13 16 15 14 13 VDD OB 1 12 VDD OB 1 12 ENABLE GND 2 11 GND ENABLE 2 11 EP EP PD VH 3 10 PD VH 3 10 IN-B OA 4 9 IN-B OA 4 9 5678 5678 ISL55110 ISL55111 (8 LD TSSOP) (8 LD TSSOP) TOP VIEW TOP VIEW VDD 1 8 OB VDD 1 8 OB PD 2 7 GND PD 2 7 GND IN-B 3 6 VH IN-B 3 6 VH IN-A 4 5 OA IN-A 4 5 OA Pin Descriptions 16 LD QFN 8 LD TSSOP PIN FUNCTION 11 VDD Logic power. 10 6 VH Driver high rail supply. 11 7 GND Ground, return for both VH rail and VDD logic supply. This is also the potential of the QFNs exposed pad (EP). 3 2 PD Power-down. Active logic high places part in power-down mode. 2- ENABLE QFN packages only. When the ENABLE pin is low, the device will operate normally (outputs controlled by the inputs). When the ENABLE pin is tied high, the output will be tri-stated. In other words, it will act as if it is open or floating regardless of what is on the IN-x pins. This provides high-speed enable control over the driver outputs. 5 4 IN-A Logic level input that drives OA to VH rail or ground. Not inverted. 4 3 IN-B, IN-B Logic level input that drives OB to VH rail or ground. Not inverted on ISL55110, inverted on ISL55111. 95 OA Driver output related to IN-A. 12 8 OB Driver output related to IN-B. 6, 7, 8, 13, 14, -NC No internal connection. 15, 16 EP - EP Exposed thermal pad. Connect to GND and follow good thermal pad layout guidelines. FN6228 Rev 8.00 Page 2 of 18 January 29, 2015 IN-A NC NC NC NC NC NC NC IN-A NC NC NC NC NC NC NC