DATASHEET ISL59920, ISL59921, ISL59922, ISL59923 FN6826 Rev 4.00 Triple Analog Video Delay Lines August 27, 2015 The ISL59920, ISL59921, ISL59922, and ISL59923 are triple Features analog delay lines that provide skew compensation between 30, 31, 46.5, or 62ns Total delay three high-speed signals. These parts are ideal for compensating for the skew introduced by a typical CAT-5, 1.0, 1.5, or 2.0ns Delay step increments CAT-6 or CAT-7 cable (with differing electrical lengths on each Very low offset voltage twisted pair) when transmitting analog video. Drop-in compatible with the EL9115 Using a simple serial interface, the ISL59920, ISL59921, Low power consumption ISL59922, and ISL59923s delays are programmable in steps of 2, 1.5, 1, or 2ns (respectively) for up to a total delay of 62, 20 Ld QFN package 46.5, 31, or 30ns (respectively) on each channel. The gain of Pb-Free (RoHS compliant) the video amplifiers can be set to x1 (0dB) or x2 (6dB) for back-termination. The delay lines require a 5V supply. Applications Skew control for RGB video signals Generating programmable high-speed analog delays 1 19 17 18 16 CENABLE 7 R 2 IN + DELAY LINE R OUT 15 + G 4 IN + DELAY LINE G 13 OUT + B 6 IN + DELAY LINE B OUT 11 + 9 X2 20 SDATA 10 SCLOCK CONTROL LOGIC 8 SENABLE BOTTOM PLATE 351C214 FIGURE 1. ISL59920, ISL59921, ISL59922, ISL59923 BLOCK DIAGRAM FN6826 Rev 4.00 Page 1 of 18 August 27, 2015 GND V SM V SP TESTR TESTB TESTG V V SMO SPO GNDISL59920, ISL59921, ISL59922, ISL59923 Ordering Information MAX TYPICAL POWER PART NUMBER PART DELAY DELAY STEP DISSIPATION PACKAGE PKG. (Notes 1, 2, 3) MARKING (ns) SIZE (ns) (mW) (RoHS Compliant) DWG. ISL59920IRZ 59920 IRZ 62 2.0 645 20 Ld 5mmx5mm QFN L20.5x5C ISL59921IR (No longer 59921 IRZ 46.5 1.5 645 20 Ld 5mmx5mm QFN L20.5x5C available or supported) ISL59922IRZ(No longer 59922 IRZ 31 1.0 645 20 Ld 5mmx5mm QFN L20.5x5C available or supported) ISL59923IRZ(No longer 59923 IRZ 30 2.0 540 20 Ld 5mmx5mm QFN L20.5x5C available or supported) NOTES: 1. Add -T* suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb- free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see product information pages for ISL59920, ISL59921, ISL59922, ISL59923. For more information on MSL, please see tech brief TB363 Pin Configuration ISL59920, ISL59921, ISL59922, ISL59923 (20 LD 5x5 QFN) TOP VIEW V 1 15 R SP OUT R 2 14 GNDO IN THERMAL GND 3 13 G OUT PAD G 4 12 V IN SMO V 5 11 B SM OUT Pin Descriptions PIN NUMBER PIN NAME PIN DESCRIPTION 1V +5V for delay circuitry and input amp SP 2R Red channel video input IN 3 GND 0V for delay circuitry supply 4G Green channel video input IN 5V -5V for input amp SM 6B Blue channel video input IN 7 CENABLE Chip Enable input, active high: logical high enables chip, low disables chip. This pin should be low at power-on until at least 30ms after the power supply has settled to within 5% of its final value. For more information, see CENABLE at Power-On on page 16. 8SENABLE Serial Enable input, active low: logical low enables serial communication 9 SDATA Serial Data input, logic threshold 1.2V: data to be programmed into chip FN6826 Rev 4.00 Page 2 of 18 August 27, 2015 B 6 20 X2 IN CENABLE 7 19 TESTR SENABLE 8 18 TESTG SDATA 9 17 TESTB SCLOCK 10 16 V SPO