DATASHEET ISL62771 FN8321 Rev 4.00 Multiphase PWM Regulator for AMD Fusion Mobile CPUs Using SVI 2.0 November 18, 2015 The ISL62771 is fully compliant with AMD Fusion SVI 2.0 and Features provides a complete solution for microprocessor and graphics Supports AMD SVI 2.0 serial data bus interface processor core power. The ISL62771 controller supports two Voltage Regulators (VRs) with three integrated gate drivers. The - Serial VID clock frequency range 100kHz to 25MHz Core VR supports 2-, or 1-phase configurations while the Dual output controller with integrated drivers Northbridge VR supports 1-phase operation. The two VRs share a Precision voltage regulation serial control bus to communicate with the AMD CPU and achieve - 0.5% system accuracy over-temperature lower cost and smaller board area compared with two-chip - 0.5V to 1.55V in 6.25mV steps solutions. - Enhanced load line accuracy The PWM modulator is based on Intersils Robust Ripple Supports multiple current sensing methods Regulator R3 Technology. Compared to traditional modulators, the R3 modulator can automatically change switching frequency - Lossless inductor DCR current sensing for faster transient settling time during load transients and - Precision resistor current sensing improved light-load efficiency. Programmable 1- or 2-phase for the core output The ISL62771 has several other key features. Both outputs Adaptive body diode conduction time reduction support DCR current sensing with single NTC thermistor for DCR temperature compensation or accurate resistor current Superior noise immunity and transient response sensing. Both outputs utilize remote voltage sense, adjustable Output current and voltage telemetry switching frequency, OC protection and power-good. Differential remote voltage sensing Applications High efficiency across entire load range AMD fusion CPU/GPU and APU core power Programmable VID offset and droop on both outputs Notebook computers Programmable switching frequency for both outputs Excellent dynamic current balance between phases Related Literature Protection: OCP/WOC, OVP, PGOOD and thermal monitor TB497, Disabling the North Bridge Regulator on the Small footprint 40 Ld 5x5 TQFN package ISL62771 - Pb-free (RoHS compliant) Core Performance 100 1.12 90 1.10 80 V = 8V IN 1.08 70 V = 12V IN 60 1.06 V = 8V IN V = 19V IN 50 1.04 40 V = 12V 1.02 IN 30 1.00 20 V = 19V IN 10 0.98 V CORE = 1.1V OUT V CORE = 1.1V OUT 0 0.96 0 5 10 15 20 25 30 35 40 45 50 55 0 5 10 15 20 25 30 35 40 45 50 55 I (A) I (A) OUT OUT FIGURE 2. V vs LOAD FIGURE 1. EFFICIENCY vs LOAD OUT FN8321 Rev 4.00 Page 1 of 35 November 18, 2015 EFFICIENCY (%) V (A) OUTISL62771 Table of Contents Simplified Application Circuit for Mid-Power CPUs . 4 CCM Switching Frequency 20 AMD Serial VID Interface 2.0 . 20 Simplified Application Circuit for Low Power CPUs 1+1 Pre-PWROK Metal VID . 20 Con-figuration . 5 SVI Interface Active . 20 VID-on-the-Fly Transition . 21 Simplified Application Circuit for Low Power CPUs 1+1 SVI Data Communication Protocol . 21 Con-figuration 6 SVI Bus Protocol 23 Block Diagram 7 Power States . 23 Dynamic Load Line Slope Trim 23 Pin Configuration 8 Dynamic Offset Trim . 24 Pin Descriptions . 8 Telemetry . 24 Ordering Information .10 Protection Features 24 Absolute Maximum Ratings 11 Overcurrent 24 Thermal Information 11 Current Balance 25 Undervoltage . 25 Recommended Operating Conditions .11 Overvoltage 25 Electrical Specifications 11 Thermal Monitor NTC, NTC NB . 25 Fault Recovery 26 Gate Driver Timing Diagram 13 Interface Pin Protection 26 Theory of Operation .14 Key Component Selection . 26 Multiphase R3 Modulator . 14 Inductor DCR Current-Sensing Network 26 Diode Emulation and Period Stretching . 15 Resistor Current-Sensing Network . 28 Channel Configuration . 15 Overcurrent Protection . 28 Power-On Reset . 15 Load Line Slope 29 Start-Up Timing . 16 Compensator . 29 Voltage Regulation and Load Line Implementation . 16 Current Balancing . 30 Differential Sensing 17 Thermal Monitor Component Selection . 30 Phase Current Balancing . 17 Layout Guidelines 31 Modes of Operation 19 Dynamic Operation 19 PCB Layout Considerations . 31 Adaptive Body Diode Conduction Time Reduction 19 Revision History . 35 Resistor Configuration Options .19 About Intersil 35 VR Offset Programming 19 FN8321 Rev 4.00 Page 2 of 35 November 18, 2015