DATASHEET ISL65426 FN6340 Rev 3.00 6A Dual Synchronous Buck Regulator with Integrated MOSFETs March 25, 2008 The ISL65426 is a high efficiency dual output monolithic Features synchronous buck converter operating over an input High Efficiency: Up to 95% voltage range of 3V to 5.5V. This single chip power solution Fixed Frequency: 1MHz provides two output voltages, which are selectable or externally adjustable from 1V to 80% of the supply voltage Operates From 3V to 5.5V Supply while delivering up to 6A of total output current. The two 1% Reference PWMs are synchronized 180 out-of-phase, reducing the Flexible Output Voltage Options RMS input current and ripple voltage. - Programmable 2-Bit VID Input The ISL65426 switches at a fixed frequency of 1MHz and - Adjustable Output From 1V to 4.0V utilizes current-mode control with integrated compensation User-Partitioned Power Blocks to minimize the size and number of external components and provide excellent transient response. The internal Ultra-Compact DC/DC Converter Design synchronous power switches are optimized for good PWMs Synchronized 180 Out-of-Phase thermal performance and high efficiency. Independent Enable Inputs and System Enable A unique power block architecture allows partitioning of six Stable All Ceramic Solutions 1A blocks to support one of four configuration options. One master power block is associated with each synchronous Excellent Dynamic Response converter channel. Four floating slave power blocks allow Independent Output Digital Soft-Start the user to assign them to either channel. Proper external Power-Good Output Voltage Monitor configuration of the power blocks is verified internally prior to soft-start initialization. Thermal-Overload Protection Overcurrent and Undervoltage Protection Independent enable inputs allow for synchronization or sequencing soft-start intervals of the two converter Pb-Free (RoHS Compliant) channels. A third enable input allows additional sequencing for multi-input bias supply designs. Individual power-good Applications indicators (PG1, PG2) signal when output voltage is within FPGA, CPLD, DSP, and CPU Core and I/O Voltages the regulation window. TM TM TM - Xilinx Spartan III , Virtex II , Virtex II Pro , TM Virtex 4 The ISL65426 integrates protection for both synchronous TM TM TM TM - Altera Stratix , Stratix II , Cyclone , Cyclone II buck regulator channels. The fault conditions include TM TM TM -Actel Fusion , LatticeSC , LatticeEC overcurrent, undervoltage, and IC thermal monitor. Low-Voltage, High-Density Distributed Power Systems High integration contained in a thin Quad Flat No-lead (QFN) package makes the ISL65426 an ideal choice to Point-of-Load Regulation power many of todays small form factor applications. A Distributed Power Systems single chip solution for large scale digital ICs, like field Set-Top Boxes programmable gate arrays (FPGA), requiring separate core and I/O voltages. Ordering Information PART TEMP. NUMBER PART RANGE PACKAGE PKG. (Note) MARKING (C) (Pb-free) DWG. ISL65426HRZ* ISL65426 HRZ -10 to +100 50 Ld 5x10 QFN L50.5x10 ISL65426IRZA* ISL65426 IRZ -40 to +85 50 Ld 5x10 QFN L50.5x10 *Add -T suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb- free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN6340 Rev 3.00 Page 1 of 22 March 25, 2008ISL65426 Pinout ISL65426 (50 LD QFN) TOP VIEW 50 49 48 47 46 45 44 43 PGND 1 PGND 42 PGND 2 PGND 41 PGND 3 PGND 40 PGND 4 PGND 39 LX1 5 38 LX6 LX1 6 37 LX6 7 PVIN1 36 PVIN6 PVIN2 8 35 PVIN5 LX2 9 34 LX5 PGND 10 PGND PGND 33 11 PGND PGND 32 12 LX3 31 LX4 PVIN3 13 30 PVIN4 14 VCC 29 PGND 15 VCC 28 PGND VCC 16 27 GND 17 PGND 26 GND 18 19 20 21 22 23 24 25 FN6340 Rev 3.00 Page 2 of 22 March 25, 2008 PGND FB1 V1SET1 EN1 V1SET2 EN2 ISET1 EN V2SET1 ISET2 V2SET2 PG1 PGND PG2 PGND FB2